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Designing ML-Resilient Locking at Register-Transfer Level

Authors:: Šišejković, D. , Collini, L. , Tan, B. , Pilato, C. , Karri, R. , Leupers, R.
Book Title:: 59th ACM/EDAC/IEEE Design Automation Conference (DAC)
Publisher:: Association for Computing Machinery
Pages:: p. 769–774
Date:: 2022
ISBN:: 978-1-45039-142-9
DOI:: 10.1145/3489517.3530541
hsb:: RWTH-2023-00056
Language:: English
Abstract:: Various logic-locking schemes have been proposed to protect hardware from intellectual property piracy and malicious design modifications. Since traditional locking techniques are applied on the gate-level netlist after logic synthesis, they have no semantic knowledge of the design function. Data-driven, machine-learning (ML) attacks can uncover the design flaws within gate-level locking. Recent proposals on register-transfer level (RTL) locking have access to semantic hardware information. We investigate the resilience of ASSURE, a state-of-the-art RTL locking method, against ML attacks. We used the lessons learned to derive two ML-resilient RTL locking schemes built to reinforce ASSURE locking. We developed ML-driven security metrics to evaluate the schemes against an RTL adaptation of the state-of-the-art, ML-based SnapShot attack.
Download:: BibTeX