Publication: Designing Trustworthy Hardware with Logic Locking 

Šišejković, D.
Ph. D. Dissertation
RWTH Aachen Univeristy
Chair for Software for Systems on Silicon
Mar. 2022


From smartphones and laptops to automotive, medical, and defense applications, microelectronic devices are deeply anchored in the modern way of life. This ever-increasing need for Hardware (HW) systems has initiated the creation of a vast landscape of electronics companies. Driven by the need to lower design and production costs to stay competitive, the operating model of the electronics industry has been transformed from an in-house business model to a global, distributed supply chain. Therefore, from early design stages to fabrication, the HW design and production flow has become reliant on third-party Intellectual Property (IP) as well as subcontracting external design houses and foundries, essentially leading to a complete loss of control over the developed HW. Consequently, the globalization process has introduced tremendous security vulnerabilities, including reverse engineering, counterfeiting, IP piracy, and malicious HW modifications known as hardware Trojans. These security challenges have triggered great interest in the academic and industrial sectors to explore novel HW design-for-trust methodologies. In particular, logic locking, a HW protection technique, has been identified as a premier method to safeguard the integrity of HW designs in the integrated circuit supply chain. Even though the security community has made efforts to design resilient locking schemes, most solutions are limited to theoretical constructs without offering a tangible route for trustworthy, industry-ready HW development. To close the gap between theoretical concepts and practical security tools, this thesis introduces a holistic approach to deploying logic locking. First, we analyze the challenge of consolidating security-relevant features of logic locking into a unified HW security metric. Second, we introduce an end-to-end logic-locking framework that enables the protection of multi-module hardware designs. The framework is further extended with a cross-module scheme that induces security dependencies between selected components to adapt the protection policies to complex HW and counteract reverse-engineering attacks. The contributions are further commercialized in the form of the MiG-V core—the first fully locked RISC-V processor available on the semiconductor market. Furthermore, a novel scheme is introduced to protect critical processor signals against the exploitation by software-controllable hardware Trojans. The proposed mechanisms are evaluated on silicon-proven processor designs through a security-cost trade-off. Finally, we investigate the challenges of logic-locking design at the frontiers of machine learning, thereby deriving a novel class of attacks and the practical foundations for the design of next-generation locking schemes.