Publication

Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

DSPACE hardware architecture for on-board real-time image/video processing in European space missions

Authors:
Saponara, S. ,  Donati, M. ,  Fanucci, L. ,  Odendahl, M. ,  Leupers, R. ,  Errico, W.
Book Title:
Real-Time Image and Video Processing Conference
Date:
Feb. 2013
Language:
English

Abstract

The increasing demand of on-board real-time image/video processing represents one of the critical issues in forthcoming scientific and commercial European space missions. To accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunication faster and faster signal and image processing algorithms are required. The only existing space-qualified European Digital Signal Processor (DSP) free of International Traffic in Arms Regulations restrictions (ATMEL TSC21020) faces a poor performance of 60 MFLOPS peak. The DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available device. Its core leverages a pipelined and massively parallel architecture based on the very long instruction word (VLIW) paradigm: 64 registers, 4 arithmetic logic units, 2 multipliers and 2 address generation units are arranged into 2 identical data-paths with cross-path capabilities. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level description and then refined at RTL level. A Xilinx-XC5VLX110 FPGA is chosen to realize an engineering prototype, providing an easy migration to the space-qualified Xilinx-XQR5VFX130 FPGA. Finally, first synthesis results on ATMEL 180 nm standard cell ASIC technology show an area of around 300 kgates and a peak performance of 1 GOPS and 750MFLOPS at 125MHz.

Download

BibTeX