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Exploiting Scalable CGRA Mapping of LU for Energy Efficiency using the LAYERS Architecture

Authors:
Rákossy, Z. E. ,  Stengele, D. ,  Ascheid, G.Leupers, R. ,  Chattopadhyay, A.
Book Title:
Intl. Conf. on Very Large Scale Integration (VLSI-SoC)
Publisher:
IEEE
Pages:
p.p. 337 - 342
Address:
Daejeon, Korea
Date:
Oct. 2015
DOI:
10.1109/VLSI-SoC.2015.7314440
Language:
English

Abstract

A scalable and highly efficient numerical linear algebra kernel mapping for coarse-grained reconfigurable architectures is proposed and applied to a 3D reconfigurable architecture, Layers, which exploits functional parallelism and a functional reconfiguration-based programming model to achieve flexibility,
scalability and low energy. Instead of solving the complex problem of mapping an application to fit architectural constraints, in our approach we tailor the mapping scheme for efficiency and scalability and exploit architectural flexibility and reconfigurability to adapt the architecture to match the derived mapping. Thus, kernel execution reaches asymptotically optimal efficiency for
various architectural parameters and input matrix sizes, without modification of the derived mapping. Detailed performance and power evaluations were done with input data sets with matrix sizes ranging from 64×64 to 16384×16384. Twelve architectural variants with up to 10×10 processing elements were used to
explore scalability of the mapping and the architecture, achieving <10% energy increase for architectures up to 8×8 PEs, coupled with performance speed-ups of more than an order of magnitude.

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