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Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

Authors:
Rai, S. ,  Garg, S. ,  Pilato, C. ,  Herdt, V. ,  Moussavi, E.Šišejković, D. ,  Karri, R. ,  Drechsler, R. ,  Merchant, F. ,  Kumar, A.
Book Title:
Proceedings of the Conference on Design, Automation & Test in Europe (DATE)
Publisher:
IEEE
Status:
accepted for publication
Date:
2021
Language:
English

Abstract

With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits thus represent high risks for both---the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks.
In this work, we will discuss IP protection measures from multiple perspectives---from system-level down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as DNA-based logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.

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