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Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms

Paolucci, P. S. ,  Biagioni, A. ,  Murillo, L. G. ,  Rousseau, F. ,  Schor, L. ,  Tosoratto, L. ,  Bacivarov, I. ,  Buecs, R. ,  Deschamps, C. ,  El Antably, A. ,  Ammendola, R. ,  Fournel, N. ,  Frezza, O. ,  Leupers, R. ,  Lo Cicero, F. ,  Lonardo, A. ,  Martinelli, M. ,  Pastorelli, E. ,  Rai, D. ,  Rossetti, D. ,  Simula, F. ,  Thiele, L. ,  Vicini, P. ,  Weinstock, J. H.
Elsevier Journal of Systems Architecture


Abstract In the next decade, a growing number of scientific and industrial applications will require power-efficient systems providing unprecedented computation, memory, and communication resources. A promising paradigm foresees the use of heterogeneous many-tile architectures. The resulting computing systems are complex: they must be protected against several sources of faults and critical events, and application programmers must be provided with programming paradigms, software environments and debugging tools adequate to manage such complexity. The EURETILE (European Reference Tiled Architecture Experiment) consortium conceived, designed, and implemented: 1- an innovative many-tile, many-process dynamic fault-tolerant programming paradigm and software environment, grounded onto a lightweight operating system generated by an automated software synthesis mechanism that takes into account the architecture and application specificities; 2- a many-tile heterogeneous hardware system, equipped with a high-bandwidth, low-latency, point-to-point 3D-toroidal interconnect. The inter-tile interconnect processor is equipped with an experimental mechanism for systemic fault-awareness; 3- a full-system simulation environment, supported by innovative parallel technologies and equipped with debugging facilities. We also designed and coded a set of application benchmarks representative of requirements of future HPC and Embedded Systems, including: 4- a set of dynamic multimedia applications and 5- a large scale simulator of neural activity and synaptic plasticity. The application benchmarks, compiled through the EURETILE software tool-chain, have been efficiently executed on both the many-tile hardware platform and on the software simulator, up to a complexity of a few hundreds of software processes and hardware cores.



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