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Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic

Authors:: Merchant, F. , Nimash, C. , Nandy, S. K. , Narayan, R.
Book Title:: VLSI Design
Pages:: p.p. 415--420
Date:: 2016
ISBN:: 978-1-46738-700-2
DOI:: 10.1109/VLSID.2016.113
Language:: English
Abstract:: In this paper we present different optimization techniques on look-up table based algorithms for double precision floating point arithmetic. Based on our analysis of different look-up table based algorithms in the literature, we re-engineer basics blocks of the algorithms (i.e. Multiplier (s) and adder (s)) to facilitate area and timing benefits to achieve higher performance. We propose different look-up table optimization techniques for the algorithms. We also analyze trade-off in employing exact rounding (0.5ulp) (unit in the last place) in the double precision floating point unit. Based on performance and extensibility criteria we take algorithms proposed by Wong and Goto as a base case to validate our optimization techniques and compare the performance with other algorithms in the literature. We improve the performance (latency × area) of Wong and Goto division algorithm by 26.94%.
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