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Software Compilation Techniques for MPSoCs

Authors:: Leupers, R. , Sheng, W. , Castrillon, J.
Editors:: Bhattacharyya, S. , Deprettere, E. , Leupers, R. , Takala, J.
Publisher:: Springer
Page(s):: 639--678
Volume:: Heidelberg
number:: 10.1007/978-1-4419-6345-1_23
Date:: 2010
ISBN:: 978-1-44196-344-4
Language:: English
Abstract:: The increasing demands such as high-performance and energy-efficiency for future embedded systems result in the emerging of heterogeneous Multiprocessor System-on-Chip (MPSoC) architectures. To fully enable the power of those architectures, new tools are needed to take care of the increasing complexity of the software to achieve high productivity. An MPSoC compiler is the tool-chain to tackle the problems of expressing parallelism in applications' modeling/programming, mapping/scheduling and generating the software to distribute on an MPSoC platform for efficient usage, for a given (pre-)verified MPSoC platform. This chapter talks about the various aspects of MPSoC compilers for heterogeneous MPSoC architectures, using a comparison to the well-established uni-processor C compiler technology. After a brief introduction to MPSoC and MPSoC compilers, the important ingredients of the compilation process, such as programming models, granularity and partitioning, platformdescription, mapping/scheduling and code-generation, are explained in detail. As the topic is relatively young, a number of case studies from academia and industry are selected to illustrate the concepts at the end of this chapter.
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