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Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS

Authors:: Joseph, J. M. , Mey, M. , Ehlers, K. , Blochwitz, C. , Winker, T. , Pionteck, T.
Book Title:: International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Pages:: p.p. 1-8
Date:: 2017
DOI:: 10.1109/RECONFIG.2017.8279785
Language:: English
Abstract:: This paper presents a design space exploration for a hardware/software co-design of a pose estimation algorithm targeting embedded systems. To fulfill resource and performance constraints, the design space is gradually explored. First, the performance is optimized in multiple steps and then, second, the resource utilization is reduced using Vivado HLS. Plus, data transport overhead of different protocols is evaluated since in this application latency is more relevant than throughput. In addition, the hardware accelerators are integrated into a software system. As hardware platform a Xilinx Zynq FPGA with a ARM dual core A-9 is used. A speedup of 2-2.5 in comparison to an optimized software solution is achieved while efficiently using the small FPGA's resources enabling pose estimation on embedded systems with 30fps.
Download:: BibTeX