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Hardware-accelerated pose estimation for embedded systems using Vivado HLS

Authors:: Joseph, J. M. , Winker, T. , Ehlers, K. , Blochwitz, C. , Pionteck, T.
Book Title:: International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Pages:: p.p. 1-7
Date:: 2016
DOI:: 10.1109/ReConFig.2016.7857173
Language:: English
Abstract:: The focus of this work is to facilitate pose estimation and, thus, gesture recognition for embedded systems, although these are tasks with high computational performance requirements. Therefore, an existing pose estimation algorithm is optimized for Xilinx High Level Synthesis (HLS). The resulting hardware acceleration cores are compared for different optimizations and, finally, we propose a hardware/software system design for a Xilinx Zynq Zedboard. Using this method, we achieve a speedup of 1.6 in comparison to a software solution on the ARM processor and, thus, facilitate hand tracking for embedded systems with low power consumption.
Download:: BibTeX