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Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

Authors:: Joseph, J. M. , Blochwitz, C. , Pionteck, T. , García-Ortiz, A.
Book Title:: Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC)
Pages:: p.p. 1-4
Date:: 2015
DOI:: 10.1109/NORCHIP.2015.7364370
Language:: English
Abstract:: In this paper, optimizations for asymmetric Network-on-Chip (NoC) router architectures are proposed for heterogeneous 3D-System-on-Chips (SoCs). The optimizations cover buffer reorganization among dies and focus on power and area savings. The architectures are compared to conventional, symmetric routers on the bases of synthesizable RTL models. Area savings of 8.3% and power savings of 5.4% for link buffers are achieved while accepting a minor average system performance loss of 2.1% in simulations. We thereby demonstrate the potentials of asymmetric NoC designs for heterogeneous 3D-SoCs.
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