Institute for Communication Technologies and Embedded Systems

MPSoC power-performance trade-off : strategies for SW mapping optimisation

Führ (Onnebrink), G.
Ph. D. Dissertation
RWTH Aachen Univeristy
chair for Software for Systems on Silicon
Mar. 2021
The ever-increasing computational workload enforces new design approaches for Hardware (HW) and Software (SW). Within the embedded domain, Multi-Processor Systems-on-Chip (MPSoCs) are seen as a feasible solution. Writing applications for MPSoCs force developers to consider increased hardware intricacies, such as Process-ing Element (PE) communication, complex memory hierarchies, bus contention, as well as frequency and voltage settings. Besides, the challenges of parallel programming add additional effort compared to writing traditional sequential applications. Finding the best power-performance trade-off is one of the most critical challenges of embedded SW development. On the one side, an efficient parallel implementation of the applications is required. On the other hand, methods to influence the trade-off need to make profitable use of process-to-PE mapping, selection of low power modes, and Dynamic Voltage and Frequency Scaling (DVFS) setting. This thesis tackles these three challenges by providing strategies for a power-performance optimised SW application mapping. Abstract power models for PEs, memories and Field Programmable Gate Arrays (FPGAs) support the power-awareness of the algorithms. The overall estimation error is 9 % for the PE power model (median of the Root-Mean-Square (RMS) error distribution). The memory power modelling approach achieves median estimation errors of 15 % (Dynamic Random-Access Memory (DRAM)) and 11 % (Static Random-Access Memory (SRAM)). The proposed FPGA power model estimates with a median error of 8 %.In order to enable comprehensive power-performance co-optimised application development, heuristics are presented for three Single-Objective Optimisation Problems (SOOPs) and two Multi-Objective Optimisation Problems (MOOPs). The first SOOP addresses PE power consumption minimisation. The power-aware mapping heuristic minimises the average PE power consumption while meeting real-time and performance constraints. A mathematical discussion and optimal solution calculation revealed that the heuristic is 19 % away from the optimum. However, the heuristic computes at least 700 × faster. The second SOOP focuses on the optimisation of memory power consumption. The minimisation is based on task graph transformations and task-to-PE mapping. The third SOOP considers FPGA accelerated MPSoCs for power-performance optimised HW/SW partitioning. A representative case study reveals an energy reduction potential of 71 % on average when compared to the non-partitioned sequential execution. The first addressed MOOP consists of a two-dimensional optimisation approach, calculating an approximation of the Pareto front. A population-based heuristic optimises the two objectives application performance and PE power consumption. The second MOOP is a three-dimensional optimisation heuristic which solves the simultaneous optimisation of the application performance, PE power consumption and memory power consumption. The quality, performance and consistency are compared against a state-of-the-art Evolutionary Multi Objective Algorithm (EMOA) implementation. Overall, the two heuristics are at least 18 × faster, while the Pareto front quality is comparable to that of the EMOA.