Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

Memory Power-Performance Trade-Off based on SW Task Mapping and Graph Transformation

Authors:: Führ (Onnebrink), G. , Aramburú, J. , Leupers, R. , Eusse, J. F.
Book Title:: The Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores
Date:: Jan. 2020
hsb:: RWTH-2021-06726
Language:: English
Abstract:: The contribution of memory power consumption can no longer be neglected for today’s heterogeneous multi-processor systems-on-chip. In addition, the hardware and software complexity necessitates fast and accurate compiler technology for determining the trade-off between performance and power. To cope with both constraints, this paper proposes a heuristic for automatic task-to-processor mapping based on task graph transformations. Moreover, a novel memory power model enables the power-driven optimisation. The approach is integrated into a commercially available framework for a detailed evaluation and tested against representative benchmarks on two diff erent platforms. Developed to minimise memory power under performance and power budget constraints, a reduction of up to 34 % memory power is possible, while the combined power consumption of the processor and the memory is decreased by 27 %. Further, the comparison with a processor power minimising approach rounds of the evaluation.
Download:: BibTeX