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Designing High-Throughput Hardware Accelerator for Stream Cipher HC-128

Authors:: Chattopadhyay, A. , Khalid, A. , Maitra, S. , Raizada , S.
Book Title:: International Symposium on Circuits and Systems (ISCAS 2012), May 20 -23, Seoul, Korea
Pages:: p.p. 1448 - 1451
Date:: 2012
DOI:: 10.1109/ISCAS.2012.6271518
Language:: English
Abstract:: Due to ubiquitous deployment of embedded systems, security and privacy are emerging as major design concerns. For that purpose, new stream ciphers are being proposed by the cryptographic researchers. HC-128 is one of the recent stream ciphers that received attention after its selection as an eStream candidate. Till date, the cipher is believed to have a good security margin. In this paper we study several implementation issues for HC-128 in a disciplined manner. We first discuss the experience on embedded and customizable processors. Then we consider the ASIC implementation for co-processor design. Further we explore several parallelization strategies for faster execution of the cipher. To the best of our knowledge such a detailed implementation exercise has not been presented in the literature. Our novel implementation strategies mark the fastest HC-128 execution reported till date.
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