Institute for Communication Technologies and Embedded Systems

Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting

Authors:
Ceng, J. ,  Sheng, W. ,  Hohenauer, M. ,  Leupers, R.Ascheid, G.Meyr, H.
Journal:
Journal of VLSI Signal Processing
Volume:
43
Page(s):
235-246
number:
2-3
Date:
Jun. 2006
Language:
English
Abstract:
Today's Application Specific Instruction-set Processor (ASIP) design methodology often employs centralized Architecture Description Language (ADL) processor models, from which software tools, such asCcompiler, assembler, linker, and instruction-set simulator, can be automatically generated. Among these tools, the C compiler is becoming more and more important. However, the generation of C compilers requires high-level architecture information rather than low-level details needed by simulator generation. This makes it particularly difficult to include different aspects of the target architecture into one single model, and meanwhile keeping consistency.

This paper presents a modeling style, which is able to capture high- and low-level architectural information at the same time and make it possible to drive both the C compiler and the simulator generation without sacrificing
the modeling flexibility. The proposed approach has been successfully applied to model a number of contemporary, real-world processor architectures.
Download:
BibTeX

Copyright © by ICE
ceng06.pdf
This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.