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S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go?

Authors:
Batina, L. ,  Jakobović, D. ,  Picek, S. ,  de la Piedra, A. ,  Šišejković, D.
Journal:
International Conference on Cryptology in India (Indocrypt)
Publisher:
Springer International Publishing
Page(s):
322--337
Date:
2014
DOI:
10.1007/978-3-319-13039-2_19
Language:
English

Abstract

In the last few years, several practitioners have proposed a wide range of approaches for reducing the implementation area of the AES in hardware. However, an area-throughput trade-off that undermines high-speed is not realistic for real-time cryptographic applications. In this manuscript, we explore how Genetic Algorithms (GAs) can be used for pipelining the AES substitution box based on composite field arithmetic. We implemented a framework that parses and analyzes a Verilog netlist, abstracts it as a graph of interconnected cells and generates circuit statistics on its elements and paths. With this information, the GA extracts the appropriate arrangement of Flip-Flops (FFs) that maximizes the throughput of the given netlist. In doing so, we show that it is possible to achieve a 50 % improvement in throughput with only an 18 % increase in area in the UMC 0.13

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