Institute for Communication Technologies and Embedded Systems

Compiled simulation of programmable DSP architectures

Authors:
Zivojnovic, V. ,  Tjiang, S. ,  Meyr, H.
Book Title:
Proc. of IEEE Workshop on VLSI Signal Processing
Pages:
p.p. 187-196
Address:
Sakai, Osaka
Date:
Oct. 1995
Language:
English
Abstract:
This paper presents a technique for simulating processors based on the principle of compiled simulation. Unlike existing, commercially available instruction set simulators for DSPs, which are of interpretive character, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware/software trade-offs before any hardware implementation. Moreover, the user can tailor the compiled simulation to trade speed for more accuracy. In this paper, the sources of the speedup and the limitations of the technique are analyzed and the realization of the simulation compiler is presented.
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