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Combined MPSoC Task Mapping and Memory Optimization for Low-Power

Authors:
Strobel, M. ,  Führ (Onnebrink), G. ,  Radetzki, M. ,  Leupers, R.
Book Title:
IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)
Pages:
p.p. 121-124
Address:
Bangkok, Thailand
Date:
Nov. 2019
DOI:
10.1109/APCCAS47518.2019.8953133
hsb:
RWTH-2020-01671
Language:
English

Abstract

The combination of processor and memory optimization in low-power multiprocessor system-on-chip software design unfolds new opportunities and allows for better results. This paper discusses the steps towards such a design flow with respect to required individual building blocks. Presented experimental results for a quad-core platform and a set of representative benchmarks support our proposed approach. On average, we achieve 8.6% power reduction and 16.2% less energy consumption compared to a state-of-the-art performance-optimized baseline using an industrial SW mapping framework.

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