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Parameterized Posit Arithmetic Hardware Generator

Authors:
Chaurasiya, R. ,  John, G. ,  Shrestha, R. ,  Jonathan, N. ,  Sangeeth, N. ,  Kaustav, N. ,  Merchant, F.Leupers, R.
Book Title:
Proceedings of the International Conference on Computer Design (ICCD)
Pages:
p. 8
Status:
accepted for publication
Date:
2018
Language:
English

Abstract

Hardware implementation of floating point arith- metic units (FPUs) has been a key area of research due to their massive hardware and energy footprints. Recently, there is a proposal to replace IEEE 754-2008 technical standard compliant floating point arithmetic units with Posit Arithmetic Units (PAUs) due to the greater accuracy, speed, and simpler hardware design of posit arithmetic. In this paper, we present the architecture of a parameterized PAU generator that can generate a PAU adder and PAU multiplier of any bit-width pre-synthesis. We synthesize arithmetic units generated using the parameterized PAU generator for 8-bit, 16-bit, and 32-bit adders and multipliers and compare them with IEEE 754-2008 compliant adders and multipliers. Both Field Programmable Gate Array (FPGA) synthesis and Application Specific Integrated Circuit (ASIC) synthesis are performed. In our comparison of m-bit PAU units with n-bit IEEE 754-2008 compliant units, it is observed that the area and energy of a PAU adder and multiplier are comparable to their IEEE 754-2008 compliant counterparts where m = n. We argue that an n-bit IEEE 754-2008 adder and multiplier can be safely replaced with an m-bit PAU adder and multiplier where m < n, due to superior numerical accuracy of the PAU; we also compare m-bit PAU adders and multipliers with n-bit IEEE 754-2008 compliant adders and multipliers. As an application example, we report performance in the domain of signal processing with and without PAU adders and multipliers, and show the advantage of our approach.

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