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Black box power estimation for digital signal processors using virtual platforms

Authors:
Führ (Onnebrink), G. ,  Schürmans, S. ,  Walbroel, F. ,  Leupers, R. ,  Ascheid, G. ,  Chen, X. ,  Harn, Y.
Book Title:
Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Series:
RAPIDO '16
Date:
Jan. 2016
DOI:
10.1145/2852339.2852345
Language:
English
Abstract:
Complex many-core architectures are seen as the solution to tackle the computational workloads of the next years. To find the best trade-off between power and performance, different processor architectures have to be considered and evaluated in a thorough and power-aware design space exploration. This is highly facilitated by electronic system level (ESL) using virtual platforms. However, state-of-the-art methods of estimating power consumption require insight into the models of the platform. Or in case no insight is necessary, they are limited to only RISC architectures. The former requirement is in conflict with widely used proprietary models shipped as binary objects, i.e. black boxes.
The methodology in this paper deals with both issues by enabling ESL black box power estimation for digital signal processors (DSP) using semi-automatic calibrated power models. Additionally, a case study reveals a high accuracy with a power estimation error of less than 4% for the Black-Fin 609 DSP on the FinBoard.
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