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Direct FPGA-based Power Profiling for a RISC Processor

Cosmin, C.-G. ,  Marcu, M. ,  Wang, Z. ,  Chattopadhyay, A. ,  Amaricai, A. ,  Fedeac, S. ,  Ghenea, M. ,  Weinstock, J. H.Leupers, R.
Book Title:
IEEE International Instrumentation and Measurement Technology Conference (I2MTC)
p.p. 1578 - 1583
Pisa, Italy
May. 2015


This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase , using FPGA imple mentation and physical measurements . I n order to determin e the power consumption at instruction - level, several programs have been developed and run on the processor implementation on FPGA . The experiments have focused at the following groups of instruction s: arithmetic and logic (ALU) instructions, memory access instructions, control instructions, compare and move instructions. The main goal of our work is the investigation of the correlation between dynamic power consumption of a RISC processor design implemen ted in different technologies (FPGA vs. ASIC) and manufacturing process es, called power technology gap . The achieved correlation coefficient between the FPGA 45nm physical power measurements and ASIC 45nm power estimation is 86.39%