Institute for Communication Technologies and Embedded Systems

Parallelisierung des Viterbi-Decoders: Algorithmus und VLSI-Architektur

Authors:
Fettweis, G.
Ph. D. Dissertation
 
School:
RWTH Aachen University
Adress:
Institute for Integrated Signal Processing Systems
Number:
ISBN 3-18-144410-3
Date:
1990
Language:
German
Download:
BibTeX