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Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition

Authors:: Auras-Rodriguez, M. H. , Zimmermann, A. , Ascheid, G. , Leupers, R.
Book Title:: Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
Publisher:: ACM
Series:: PARMA-DITAM '17
Pages:: p.p. 13--18
Address:: New York, NY, USA
Date:: 2017
ISBN:: 978-1-45034-877-5
DOI:: 10.1145/3029580.3029583
Language:: English
Abstract:: In this paper, we present a novel approach that assists in the task of data-parallel pattern recognition. The classification of program code into parallel patterns relies mainly in the extraction of characteristics that describe memory access operations. Our tool automatically generates static decidable memory access characterizations using a Program Expression Graph (PEG) representation of input programs. We analyze the main properties of PEGs that favor the corresponding extraction algorithm in comparison to other input representations. Additionally, we demonstrate the effectiveness of our proposed method using the PolyBench kernels for the recognition of the data-parallel patterns that drive the Bones skeleton-based parallellizing compiler, targeting as case study modern embedded platforms (i.e. Keystone II and Parallella Board).
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