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Investigation of localized thermal vias for temperature reduction in 3D multicore processors

Authors:: Zajac, P. , Galicia, M. , Maj, C. , Napieralski, A.
Booktitle:: 2015 22nd International Conference Mixed Design of Integrated Circuits Systems (MIXDES)
Page(s):: 426-430
Date:: 2015
DOI:: 10.1109/MIXDES.2015.7208556
Language:: English
Abstract:: 3D stacking of integrated circuits is a promising idea for increasing the processor performance. However, the major challenge is overcoming thermal issues due to excessive power density. In this paper, using Intel s Haswell processor as an example, we analyze the thermal behavior of an eight-core processor implemented as a 2D chip and as a 3D architecture with two layers. We also investigate the use of localized thermal vias for improving the thermal behaviour of the 3D stack. We show that the peak temperature can be significantly reduced (by 5.8°C in our case) due to the implementation of thermal vias.
Download:: BibTeX