Publications
Latest Publications
Copic, M., Leupers, R. and Ascheid, G.:
Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling,
in Integration, the VLSI Journal,
Vol. 70,
Elsevier,
pp.
10-20,
Jan. 2020, 10.1016/j.vlsi.2019.09.004
Jünger, L., Bölke, J., Tobies, S., Hoffmann, A. and Leupers, R.:
ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms,
in
Proceedings of the Conference on Design, Automation & Test in Europe (DATE),
2020, accepted for publication ©2020 IEEE
Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA,
in (Integration),
Vol. 69,
Elsevier,
pp.
50-61,
Nov. 2019, 10.1016/j.vlsi.2019.09.005
Strobel, M., Führ (Onnebrink), G., Radetzki, M. and Leupers, R.:
Combined MPSoC Task Mapping and Memory Optimization for Low-Power,
in
IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)(Bangkok, Thailand),
Nov. 2019 ©2019 IEEE
Ayad, A., Zamani, A., Schmeink, A. and Dartmann, G.:
Design and Implementation of a Hybrid Anomaly Detection System for IoT,
in
Sixth International Conference on Internet of Things: Systems, Management and Security (IOTSMS),
IEEE,
Oct. 2019, accepted for publication ©2019 IEEE
Machhamer, R., Dziubany, M., Czenkusch, L., Laux, H., Schmeink, A., Gollmer, K.-U., Naumann, S. and Dartmann, G.:
Online Offline Learning for Sound-based Indoor Localization Using Low-cost Hardware,
in
IEEE Access,
Oct. 2019, 10.1109/ACCESS.2019.2947581 ©2019 IEEE
Peine, A., Hallawa, A., Schöffski, O., Dartmann, G., Begic Fazlic, L., Schmeink, A., Marx, G. and Martin, L.:
A Deep Learning Approach for Managing Medical Consumable Materials in Intensive Care Units via Convolutional Neural Networks: Technical Proof-of-Concept Study,
in JMIR Med Inform,
Vol. 7,
No. 4,
p.
e14806,
Oct. 2019, ISSN: 2291-9694, 10.2196/14806
Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.:
Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs,
in (IEEE ESL),
Vol. 11,
No. 3,
pp.
93-96,
Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE
Hauck, M., Machhamer, R., Czenkusch, L., Gollmer, K.-U. and Dartmann, G.:
Node and Block-based Development Tools for Distributed Systems with AI Applications,
in
IEEE Access,
Sep. 2019, 10.1109/ACCESS.2019.2940113 ©2019 IEEE
Dartmann, G. (Ed.), Song, H. (Ed.) and Schmeink, A. (Ed.):
Big Data Analytics for Cyber-Physical Systems,
Elsevier,
Jul. 2019, accepted for publication, ISBN: 978-0-12816-637-6
Topal, O. A., Demir, , Dartmann, G., Schmeink, A., Ascheid, G., Pusane, A. E. and Karabulut Kurt, G.:
Physical Layer Spoofing Against Eavesdropping Attacks,
in
The 8th Mediterranean Conference on Embedded Computing - MECO'2019 ,
pp.
1-5,
Jun. 2019, ISSN: 2377-5475, 10.1109/MECO.2019.8760168 ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.:
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries,
in 24th IEEE European Test Symposium (ETS'19),
May. 2019, accepted for publication ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.:
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans,
in Great Lakes Symposium on VLSI (GLSVLSI'19),
May. 2019, 10.1145/3299874.3317983 ©2019 IEEE
Bytyn, A., Leupers, R. and Ascheid, G.:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration,
in
2019 IEEE International Symposium on Circuits and Systems (ISCAS)
,
IEEE,
May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.:
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms,
in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT),
Apr. 2019
