ICE student Evgenii Rezunov wins Best Bachelor Award

November 22, 2022

Due to his extraordinary work during his bachelor's, Evgenii Rezunov is awarded the Rohde & Schwarz Best Bachelor award.

On the "Tag der Elektrotechnik" he presented the remarkable work that he conducted for his bachelor's thesis on the topic:
Exploring the impact of logic locking on the information flow of cryptographic circuits.

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ICE Spin-off MachineWare is winner of the RWTH Spin-off Award

November 8, 2022

In the second round of this year's RWTH Spin-off Award  MachineWare GmbH was honored as one of the six winners. The winners represent the broad spectrum of excellent research disciplines at RWTH Aachen University. The award is the only official award given to outstanding young RWTH start-ups.

MachineWare has developed a high-speed simulator for novel microprocessors, allowing…

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ICE involved in first Cyberagency Project

September 20, 2022

The Cyberagency has announced their choices for the winner of their first project call ever. Member of the ICE staff will support Hensoldt Cyber in advising the Cyberagency about the current need for action in Germany's hardware security field. ICE's hardware security team will function as "experts of the hardware supply chain".

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ICE excursion to the University of Sarajevo

August 29, 2022

During August 25/26, 2022 the ICE team visited the Faculty of Electrical Engineering Sarajevo. After a short introduction of both parties, each group gave short presentations on their field of research.

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New Book: 3D Interconnect Architectures for Heterogeneous Technologies

July 25, 2022

A new book with the title “3D Interconnect Architectures for Heterogeneous Technologies: Modeling and Optimization” has been published by Jan Moritz Joseph from ICE. It describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration.…

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Press release: Aachen-based start-up MachineWare enables ultra-fast RISC-V simulation

June 28, 2022

Startup MachineWare is set to revolutionise semiconductor design with its high-speed RISC-V simulator SIM-V.

SIM-V Compute aims to design and verify high-performance RISC-V systems, including hardware models of GPUs and high-speed PCIe interconnects.
SIM-V Edge, at the other end of the spectrum, is optimised for designing compact 32-bit edge computing systems and offers a wide range…

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ICE organized the 4th version of hardware security workshop at HiPEAC 2022

June 27, 2022

For the fourth time in a row, ICE organized the Workshop on Secure Hardware, Architectures, and Operating Systems (SeHAS) at the HiPEAC (https://www.hipeac.net/2022/budapest/#/) conference - this time in Budapest. 

The agenda was packed with top-notch talks in the domain of security, ranging from the application of formal methods to ensure secure hardware implementations down to…

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Jülich-Aachen Neuromorphic Computing Day

May 25, 2022

at Forschungszentrum Jülich

Highlights of the Projects NEUROTEC and NeuroSys

• Prof. Rainer Waser (Forschungszentrum Jülich, RWTH Aachen University)
  Neuro-inspired Technology of Artificial Intelligence for Future Electronics: NEUROTEC
   
• Prof. Max Christian Lemme (RWTH Aachen University, AMO GmbH)
  Clusters4Future NeuroSys– Neuromorphic Hardware for Autonomous Systems of Artificial…

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New Spin Off MachineWare GmbH founded

May 3, 2022

MachineWare is a provider of high-speed instruction set simulators, including RISC-V full-system simulators. Its technologies enable ultra-fast software bring-up and validation before physical hardware is available. It's headquartered in Aachen, Germany.

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ICE Receives Best Paper Award at ISQED 2022

April 7, 2022

ICE researchers Dr. Melvin Galicia Cota, Dr. Farhad Merchant, and Prof. Rainer Leupers received the best paper award at International Symposium on Quality Electronic Design 2022 (ISQED 2022) for the paper entitled "A Parallel SystemC Virtual Platform for Neuromorphic Architectures." The paper presents a parallel SystemC-based virtual prototype for RISC-V multicore platforms…

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