Institute for Communication Technologies and Embedded Systems

EURETILE

SSS is partner of the European FP7 Project EURETILE (EUropean REference TIled architecture Experiment), which has the goal to investigate and implement a brain-inspired massively parallel tiled computer architecture. The focus of SSS in EURETILE is the development of an efficient MPSoC simulation environment, which will be suitable for application development, software debugging and performance verification.

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