- Digital Signal Processors, in Handbook of Networked and Embedded Control Systems pp. 279–294, Birkhäuser, 2005.
- Witte, E. M., Chattopadhyay, A., Schliebusch, O., Kammler, D., Leupers, R., Ascheid, G., and Meyr, H.:Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation, in Proceedings of the International Conference on Computer Design (ICCD) (San Jose, California, USA), pp. 193–199, Oct. 2005.
- Retargetable Generation of TLM Bus Interfaces for MP-SoC Platforms, in 3rd IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (CODES+ISSS) (Jersey City, NJ, USA), Sept. 2005.
- Schmitt, L. and Meyr, H.:On the Asymptotics of Density Evolution for Iterative (Turbo) Decoding, in In Proc. of the 43rd Annual Allerton Conference on Communication, Control, and Computing (Monticello, IL, USA), Sept. 2005.
- Mozumdar, M., Karuri, K., Chattopadhyay, A., Kraemer, S., Scharwächter, H., Meyr, H., Ascheid, G., and Leupers, R.:Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study, in IEEE 16th International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (Samos, Greece), July 2005.
- On the Analysis of an Up/Down Power Controlled CDMA System in a Fast Rayleigh-Fading Environment, in In Proc. of IST (Dresden, Germany), June 2005.
- Schliebusch, O., Chattopadhyay, A., Witte, E. M., Kammler, D., Ascheid, G., Leupers, R., and Meyr, H.:Optimization Techniques for ADL-driven RTL Processor Synthesis, in Proceedings of the IEEE International Workshop on Rapid Systems Prototyping (RSP) (Montreal, Canada), pp. 165–171, June 2005.
- Meyr, H., Schliebusch, O., Wieferink, A., Kammler, D., Witte, E. M., Lüthje, O., Hohenauer, M., Braun, G., and Chattopadhyay, A.:Designing and Modeling MPSoC Processors and Communication Architectures, in Building ASIPs: The Mescal Methodology (Gries, M. and Keutzer, K., eds.) ch. 7, pp. 229–280, Springer, June 2005.
- Fine-grained Application Source Code Profiling for ASIP Design, in 42nd Design Automation Conference (Anaheim, California, USA), June 2005.
- FFT processor: a case study in ASIP development, in Proceedings of the IST Mobile & Wireless Communications Summit (Dresden, Germany), June 2005.
- Application Specific Processors for Flexible Receivers, in Proc. of National Symposium of Radio Science (URSI) (Poznan (Poland)), Apr. 2005.
- A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) (Munich, Germany), Mar. 2005.
- Improving MIMO Phase Noise Estimation by Exploiting Spatial Correlations, in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2005) (Philadelphia, PA, USA), Mar. 2005.
- C Compiler Retargeting Based on Instruction Semantics Models., in DATE (Munich, Germany), Mar. 2005.
- A Framework for Automated and Optimized ASIP Implementation Supporting Multiple Hardware Description Languages, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC) vol. 1, (Shanghai, China), pp. 280–285, Jan. 2005.
- A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platforms, in Computers & Digital Techniques vol. 152, no. 1, pp. 3–11, Jan. 2005.
- Wilhelm, R. and Leupers, R.:Backend Code Generation, in Embedded Systems Design - The ARTIST Roadmap for Research and Development ch. vol. 3436, 2005.
– Lecture Notes in Computer Science –.
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The award ceremony is on June 20, 2017
Area: Application Specific Computing Systems and Hardware Architectures
We are glad to announce that the EC will grant the H2020 Innovation Action TETRAMAX with