Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models

Authors:
Jan Henrik Weinstock, Rainer Leupers, and Gerd Ascheid
Book Title:
Proceedings of the 2017 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
Address:
Stockholm, Sweden
Date:
Jan. 2017
Language:
English

BibTeX

@inproceedings{weinstock-rapido-2017,
author = {Jan Henrik Weinstock, Rainer Leupers, and Gerd Ascheid},
booktitle = {Proceedings of the 2017 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools},
title = {Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models},
year = {2017},
month = {jan},
address = {Stockholm, Sweden},
}

Abstract

High simulation speed is always a concern for developers of virtual platforms, especially given the ever increasing number of processors in modern designs. On the one hand, parallel simulation has appeared as a promising candidate, but has yet to be fully studied in realistic virtual platforms such as those deployed by the industry today. On the other hand, omission of unneeded simulation details, such as skipping simulation of processors in idle or low-power states, also improves performance.

This work studies both approaches combined in a realistic virtual platform, achieving average performance gains of 3.2x over sequential simulation.

Download

No download found.

News >> News >> News

Miguel Angel Aguilar wins the ICT Young Researcher Award 2017

The profile area "Information and Communication Technology (ICT)" at RWTH Aachen

New European initiative TETRAMAX has officially been kicked-off!

With its kick-off meeting on 19 September in Aachen, TETRAMAX (TEchnology TRAnsfer via

User login

Login

Forgot your password?