Multi-Grained Performance Estimation for MPSoC Compilers

Authors:
Miguel Angel Aguilar, Abishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jeronimo Castrillon, and Liam Fitzpatrick
Book Title:
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Publisher:
ACM
Address:
Seoul, Republic of Korea
Pages:
14:1–14:2
Date:
Oct. 2017
ISBN:
978-1-45035-184-3
DOI:
10.1145/3125501.3125521
Language:
English

BibTeX

@inproceedings{aguilar17c,
author = {Miguel Angel Aguilar, Abishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jeronimo Castrillon, and Liam Fitzpatrick},
booktitle = {International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)},
title = {Multi-Grained Performance Estimation for MPSoC Compilers},
year = {2017},
month = {oct},
address = {Seoul, Republic of Korea},
pages = {14:1-14:2},
ISBN= {978-1-45035-184-3},
publisher = {ACM},
doi = {10.1145/3125501.3125521},
}

Abstract

Parallelizing compilers are a promising solution to tackle key challenges of MPSoC programming. One fundamental aspect for a profitable parallelization is to estimate the performance of the applications on the target platforms. There is a wide range of state-of-the-art performance estimation techniques, such as, simulation-based, measurement-based, among others. They provide performance estimates typically only at function or basic block granularity. However, MPSoC compilers require performance information at other granularities, such as statement, loop or even arbitrary code blocks. In this paper, we propose a framework to adapt performance information sources to any granularity required by an MPSoC compiler.

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