- Schmitt, L., Simon, V., Grundler, T., Schreyoegg, C., and Meyr, H.:Initial Synchronization of W-CDMA Systems using a Power-Scaled Detector with Antenna Diversity in Frequency-Selective Rayleigh Fading Channels, in IEEE Global Communications Conference (GLOBECOM) (San Francisco, CA, USA), Dec. 2003.
- Schulz-Rittich, P., Senst, A., Bilke, T., and Meyr, H.:The Effect of Imperfect SNR Knowledge on Multiantenna Multiuser Systems with Channel Aware Scheduling, in IEEE Global Communications Conference (GLOBECOM) (San Francisco, CA, USA), Dec. 2003.
- Ariyamparambath, M., Bussaglia, D., Reinkemeier, B., Kogel, T., and Kempf, T.:A Highly Efficient Modeling Style for Heterogeneous Bus Architectures, in International Symposium on System-on-Chip (Tampere (Finland)), Nov. 2003.
- Wieferink, A., Kogel, T., Hoffmann, A., Zerres, O., and Nohl, A.:SoC Integration of Programmable Cores, in International Workshop on IP-Based SoC Design (Grenoble, France), Nov. 2003.
- A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks, in The First IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis (Newport Beach (California USA)), Oct. 2003.
- Schulz-Rittich, P., Senst, A., Krause, U., and Meyr, H.:Increasing System Throughput with Time-Varying Beamforming in Multiuser Systems with Slowly Varying Fading Channels, in IEEE Vehicular Technology Conference Fall (VTC) (Orlando, FL, USA), Oct. 2003.
- A Wireless Revenue based Scheduler with QoS Support, in 41st Annual Allerton Conference on Communications, Control and Computing (Monticello, IL, USA), Sept. 2003.
- Leupers, R., Wahlen, O., Hohenauer, M., Kogel, T., and Marwedel, P.:An Executable Intermediate Representation for Retargetable Compilation and High-Level Code Optimization, in Int. Workshop on Systems, Architecturs, Modeling and Simulation(SAMOS) (Samos(Greece)), July 2003.
- Kogel, T., Wieferink, A., Leupers, R., Ascheid, G., Meyr, H., Bussaglia, D., and Ariyamparambath, M.:Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs, in Int.Workshop on Systems, Architectures, Modeling and Simulation (SAMOS) (Samos (Greece)), July 2003.
- Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models, in 40th Design Automation Conference (DAC) (Anaheim (USA)), June 2003.
- A Generic Toolset for SoC Multiprocessor Debugging and Synchronisation, in IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP) (The Hague (Netherlands)), June 2003.
- Netzwerkprozessoren in C programmieren, in Design&Elektronik 04/2003 (Munich), WEKA Verlag, May 2003.
- Simon, V., Schmitt, L., Grundler, T., Schreyoegg, C., and Meyr, H.:A Rake Finger Grid for Asynchronous DS-CDMA Systems Using LMMSE Tab Weight Estimation, in Proceedings of the Vehicular Technology Conference, VTC-Spring (Jeju, Korea), Apr. 2003.
- Offset Assignment Showdown:Evaluation of DSP Adress Code Optimization Algorithms, in 12th International Conf.on Compiler Construction (CC) (Warsaw, Poland), Apr. 2003.
- Falk, H., Ghez, C., Miranda, M., and Leupers, R.:High-Level Control Flow Transformations for Perfomance Improvement of Adress-Dominated Multimedia Applications, in 11th Workshopon Synthetisis and System Integration of Mixed Information Technologies (SASIMI) (Hiroshima (JAPAN)), Apr. 2003.
- Processor/Memory Co-Exploration on Multiple Abstraction Levels, in DesignAutomation&Test in Europe (Date) (Munich), Mar. 2003.
- Instruction Scheduler Generation for Retargetable Compilation, in IEEE Design&Test of Computers Jan. 2003.
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Prof. Leupers is Keynote Speaker at the 4th IEEE INTERNATIONAL SYMPOSIUM ON WIRELESS SYSTEMS"
TETRAMAX held its first Industrial Advisory Board meeting and presented the granted Technology Transfer Experiments!
On September 13 in Aachen, the TETRAMAX partners from all over Europe as well as the industrial
During May 24/25, 2018 the ICE team visited the University of Kaiserslautern and met the local