Alumni Assistant: Gereon Führ

Publications

Führ (Onnebrink), G.: MPSoC power-performance trade-off : strategies for SW mapping optimisation, Ph. D. Dissertation RWTH Aachen Univeristy, Mar. 2021, 10.18154/RWTH-2021-03407


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, ISBN: 978-3-03052-794-5, 10.1007/978-3-030-52794-5_5


Führ (Onnebrink), G., Aramburú, J., Leupers, R. and Eusse, J. F.: Memory Power-Performance Trade-Off based on SW Task Mapping and Graph Transformation, in The Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores, Jan. 2020


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005


Strobel, M., Führ (Onnebrink), G., Radetzki, M. and Leupers, R.: Combined MPSoC Task Mapping and Memory Optimization for Low-Power, in IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)(Bangkok, Thailand), pp. 121-124, Nov. 2019, 10.1109/APCCAS47518.2019.8953133 ©2019 IEEE


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Führ (Onnebrink), G., Leupers, R. and Ascheid, G.: ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models, in Proceedings of the 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools(Manchester, England), Jan. 2018, 10.1145/3180665.3180667


Führ (Onnebrink), G., Walbroel, F., Klimt, J., Leupers, R., Ascheid, G., Murillo, L. G., Schürmans, S., Chen, X. and Harn, Y.: DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Application Mapping, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2017, 10.1109/SAMOS.2017.8344628 ©2017 IEEE


Schürmans, S., Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Chen, X.: Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model, in (ACM TECS), Vol. 16, No. 1, ACM, pp. 26:1--26:26, Oct. 2016, ISSN: 1539-9087, 10.1145/2987375


Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Schürmans, S.: Black box ESL power estimation for loosely-timed TLM models, in ViPES Workshop 2016, Jul. 2016 ©2016 IEEE


Leupers, R., Schürmans, S., Aguilar, M. A. and Führ (Onnebrink), G.: Power-Aware Multicore Software Development, in Embedded World Conference 2016, Feb. 2016


Führ (Onnebrink), G., Schürmans, S., Walbroel, F., Leupers, R., Ascheid, G., Chen, X. and Harn, Y.: Black box power estimation for digital signal processors using virtual platforms, in Proceedings of the 2016 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2016, 10.1145/2852339.2852345


Schürmans, S., Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Chen, X.: ESL Power Estimation using Virtual Platforms with Black Box Processor Models, in ViPES Workshop 2015, pp. 354 - 359, Jul. 2015, 10.1109/SAMOS.2015.7363698