Alumni Assistant: Domnik Šišejković

Publications from Apr/ 2024 to 2020

• Reimann, L. M., Prashar, A., Ghinami, C., Pelke, R., Šišejković, D., Merchant, F. and Leupers, R.: QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT), Apr. 2024, accepted for publication
  
• Reimann, L. M., Wiesner, J., Šišejković, D., Merchant, F. and Leupers, R.: SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors, in 31st IFIP/IEEE Conference on Very Large Scale Integration (VLSI-SoC 2023), Oct. 2023, 10.1109/VLSI-SoC57769.2023.10321922 ©2023 IEEE
  
• Moussavi, E., Singh, A., Šišejković, D., Kumar, A., Kizatov, D., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic, in arXiv preprint arXiv:2304.05686, The 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023) , Jun. 2023, accepted for publication, 10.48550/arXiv.2304.05686 ©2023 IEEE
  
• Raj, A., Avula, N., Das, P., Šišejković, D., Merchant, F. and Acharyya, A.: DeepAttack: A Deep Learning Based Oracle-less Attack on Logic Locking, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Jan. 2023, accepted for publication
  
• Šišejković, D. and Leupers, R.: Logic Locking - A Practical Approach to Secure Hardware, Springer Cham, 1 ed., 2023, ISBN: 978-3-03119-122-0, 10.1007/978-3-031-19123-7
  
• Reimann, L. M., Erdonmez, S., Šišejković, D. and Leupers, R.: Quantitative Information Flow for Hardware: Advancing the Attack Landscape, in LASCAS 2023, Nov. 2022, 10.48550/arXiv.2211.16891
  
• Moussavi, E., Šišejković, D., Singh, A., Kizatov, D., Leupers, R., Ingebrandt, S., Pachauri, V. and Merchant, F.: A Temperature Independent Readout Circuit for ISFET-Based Sensor Application, in 2022 IEEE 23rd Latin American Test Symposium (LATS), pp. 1-4, Sep. 2022, 10.1109/LATS57337.2022.9937020
  
• Moussavi, E., Šišejković, D., Brings, F., Kizatov, D., Singh, A., Xuan , T. V., Ingebrandt, S., Leupers, R., Pachauri, V. and Merchant, F.: pHGen: A pH-Based Key Generation Mechanism Using ISFETs, in IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 61-64, Jun. 2022, 10.1109/HOST54066.2022.9840282 ©2022 IEEE
  
• Staudigl, F., Al Indari, H., Schön, D., Šišejković, D., Merchant, F., Joseph, J. M., Rana, V., Menzel, S. and Leupers, R.: NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2022, 10.23919/DATE54114.2022.9774651 ©2022 IEEE
  
• Šišejković, D.: Designing Trustworthy Hardware with Logic Locking, Ph. D. Dissertation RWTH Aachen Univeristy, Mar. 2022, 10.18154/RWTH-2022-02625
  
• Šišejković, D., Collini, L., Tan, B., Pilato, C., Karri, R. and Leupers, R.: Designing ML-Resilient Locking at Register-Transfer Level, in 59th ACM/EDAC/IEEE Design Automation Conference (DAC), p. 769–774, Association for Computing Machinery, 2022, ISBN: 978-1-45039-142-9, 10.1145/3489517.3530541 ©2022 IEEE
  
• Staudigl, F., Sturm, K. J. X., Bartel, M., Fetz, T., Šišejković, D., Joseph, J. M., Bolzani Pöhls, L. and Leupers, R.: X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation, in International Conference on Artificial Intelligence Circuits and Systems (AICAS), 2022, accepted for publication ©2022 IEEE
  
• Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD) , pp. 603-607, Oct. 2021, 10.1109/ICCD53106.2021.00097 ©2021 IEEE
  
• Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE
  
• Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389
  
• Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474132
  
• Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, 10.1109/VLSID51830.2021.00051 ©2021 IEEE
  
• Šišejković, D., Reimann, L. M., Moussavi, E., Merchant, F. and Leupers, R.: Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), 2021, 10.1109/VLSI-SoC53125.2021.9606979 ©2021 IEEE
  
• Šišejković, D. and Leupers, R.: Trustworthy Hardware Design with Logic Locking, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), IEEE, 2021, 10.1109/VLSI-SoC53125.2021.9606998 ©2021 IEEE
  
• Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, pp. 138--152, 2020, 10.1007/978-3-030-52794-5_11 ©2020 IEEE
  

>>