Jan Moritz Joseph

Biography & CV

Dr. Joseph's CV

Dr. Joseph got his B.Sc. in medical engineering in 2011 and his M.Sc. in computer science in 2014 from the Universität zu Lübeck, Germany.  From 2008 to 2014 he was a scholarship holder of the German Merit Foundation (Deutsche Studienstiftung e.V.). Dr. Joseph received his Ph.D. from Otto-von-Guericke Universität Magdeburg, Germany, in 2019. The title of his thesis was "Networks-on-Chip for heterogeneous 3D Systems-on-Chip". His Ph.D. was awarded the highest honors “summa cum laude”. In 2020, he received the award for the best PhD thesis from the Faculty of Electrical Engineering and Information Technology at Otto-von-Guericke Universität Magdeburg, Germany.

From 2019 to 2020 Dr. Joseph was a visiting researcher at Dr. Krishna’s Synergy Lab at Georgia Institute of Technology, Atlanta, GA. His stay was partially funded by a scholarship from the German Academic Exchange Service.

He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in June 2020 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon.

Research Interests

  • DNN-Accelerators
  • On-Chip Learning
  • Machine Learning
  • Simulation
  • Networks-on-Chip
  • 3D Integration

Publications

Publications from 2016 to 2014

Joseph, J. M., Wrieden, S., Blochwitz, C., García-Oritz, A. and Pionteck, T.: A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip, in 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), pp. 1-8, 2016, 10.1109/ReCoSoC.2016.7533908 ©2016 IEEE


Joseph, J. M., Blochwitz, C. and Pionteck, T.: Adaptive allocation of default router paths in Network-on-Chips for latency reduction, in International Conference on High Performance Computing Simulation (HPCS), pp. 140-147, 2016, 10.1109/HPCSim.2016.7568328 ©2016 IEEE


Joseph, J. M., Winker, T., Ehlers, K., Blochwitz, C. and Pionteck, T.: Hardware-accelerated pose estimation for embedded systems using Vivado HLS, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-7, 2016, 10.1109/ReConFig.2016.7857173 ©2016 IEEE


Joseph, J. M., Blochwitz, C., Pionteck, T. and García-Ortiz, A.: Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs, in Nordic Circuits and Systems Conference (NORCAS): NORCHIP International Symposium on System-on-Chip (SoC), pp. 1-4, 2015, 10.1109/NORCHIP.2015.7364370 ©2015 IEEE


Blochwitz, C., Joseph, J. M., Backasch, R., Pionteck, T., Werner, S., Heinrich, D. and Groppe, S.: An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases, in International Conference on ReConFigurable Computing and FPGAs (ReConFig), pp. 1-7, 2015, 10.1109/ReConFig.2015.7393291 ©2015 IEEE


Joseph, J. M. and Pionteck, T.: A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling, in International Symposium on System-on-Chip (SoC), pp. 1-6, 2014, 10.1109/ISSOC.2014.6972440 ©2014 IEEE


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