Farhad Merchant

Jobs

Students looking for BSc/MSc/PhD thesis or a HiWi job are suggested to make an appointment via email for personal visit.

Current HiWis

  • Daniyar Kizatov
  • Milos Bratic

Past Students

  • Jure Vreca (master)
  • Lukas Juenger (master)
  • Harshit Srivastava (bachelor)
  • Abhishek Adhave (bachelor)
  • Pankti Shah (bachelor -  DAAD)
  • Marwin Kirchhofs (bachelor)
  • Karl Sturm (bachelor)
  • Mohil Desai (bachelor - DAAD)
  • Masoom Panda (bachelor - DAAD)
  • Kirthihan Yasotharan (master)

Biography

Farhad Merchant received his Ph.D. from the Indian Institute of Science, Bangalore (India), in 2016. His Ph.D. thesis title was "Algorithm-Architecture Co-design for Dense Linear Algebra Computations." He received the DAAD fellowship during his PhD. He worked as a postdoctoral research fellow at Nanyang Technological University (NTU), Singapore, from March 2016 to December 2016. In December 2016, he moved to Corporate Research in Robert Bosch in Bangalore as a Researcher, where he worked on numerical methods for ordinary differential equations. He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in December 2017 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon. Farhad is the recipient of the HiPEAC technology transfer award in 2019.

Research Interests

  • Hardware Security
  • Hardware Assisted Security
  • Computer Architecture
  • Performance Modeling
  • Computer Arithmetic

Publications

Publications from Sep/ 2016 to 2014

Bhattacharjee, D., Merchant, F. and Chattopadhyay, A.: Enabling in-memory computation of binary {BLAS} using ReRAM crossbar arrays, in VLSI-SoC, Sep. 2016, ISBN: 978-1-50903-561-8, 10.1109/VLSI-SoC.2016.7753568 ©2016 IEEE


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation, in VLSI Design, pp. 98--103, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.109 ©2016 IEEE


Merchant, F., Nimash, C., Nandy, S. K. and Narayan, R.: Efficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic, in VLSI Design, pp. 415--420, 2016, ISBN: 978-1-46738-700-2, 10.1109/VLSID.2016.113 ©2016 IEEE


Merchant, F., Maity, A., Mahadurkar,, M., Vatwani, K., Munje, I., Krishna C, M., Sivanandan, N., Gopalan, N., Raha, S., Nandy, S. K. and Narayan, R.: Micro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations, in VLSI Design, pp. 153--158, 2015, ISBN: 978-1-47996-658-5, 10.1109/VLSID.2015.31 ©2015 IEEE


Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Scalable and Energy-Efficient Reconfigurable Accelerator for Column-Wise Givens Rotation, in 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)(Playa-del-Carmen, Mexico), IEEE, Oct. 2014, 10.1109/VLSI-SoC.2014.7004166 ©2014 IEEE


Rákossy, Z. E., Merchant, F., Acosta Aponte, A., Nandy, S. K. and Chattopadhyay, A.: Efficient and Scalable CGRA-based Implementation of Column-wise Givens Rotation, in 25th IEEE International Conference on Application-specific Systems, Architectures and Processors(Zuerich, Switzerland), Jun. 2014, 10.1109/ASAP.2014.6868659 ©2014 IEEE


Merchant, F., Chattopadhyay, A., Garga, G., Nandy, S. K. and Narajan, R.: Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR) , in 27th International Conference on VLSI Design, IIT Bombay, Mumbai India January 7-9, pp. 258 - 263 , 2014, ISSN: 1063-9667, 10.1109/VLSID.2014.51 ©2014 IEEE


Das, S., Madhu, K., Krishna C, M., Sivanandan, N., Merchant, F., Biswas, I., Pulli, A., Nandy, S. K. and Narayan, R.: A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths., in Journal of Systems Architecture - Embedded Systems Design, Vol. 60, No. 7, pp. 592--614, 2014, 10.1016/j.sysarc.2014.06.002


Mahadurkar,, M., Merchant, F., Maity, A., Vatwani, K., Munje, I., Gopalan, N., Nandy, S. K. and Narayan, R.: Co-exploration of NLA kernels and specification of Compute Elements in distributed memory CGRAs, in SAMOS 2014, pp. 225--232, 2014, 10.1109/SAMOS.2014.6893215 ©2014 IEEE


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