Farhad Merchant

Jobs

Students looking for BSc/MSc/PhD thesis or a HiWi job are suggested to make an appointment via email for personal visit.

Current HiWis

  • Daniyar Kizatov
  • Milos Bratic

Past Students

  • Jure Vreca (master)
  • Lukas Juenger (master)
  • Harshit Srivastava (bachelor)
  • Abhishek Adhave (bachelor)
  • Pankti Shah (bachelor -  DAAD)
  • Marwin Kirchhofs (bachelor)
  • Karl Sturm (bachelor)
  • Mohil Desai (bachelor - DAAD)
  • Masoom Panda (bachelor - DAAD)
  • Kirthihan Yasotharan (master)

Biography

Farhad Merchant received his Ph.D. from the Indian Institute of Science, Bangalore (India), in 2016. His Ph.D. thesis title was "Algorithm-Architecture Co-design for Dense Linear Algebra Computations." He received the DAAD fellowship during his PhD. He worked as a postdoctoral research fellow at Nanyang Technological University (NTU), Singapore, from March 2016 to December 2016. In December 2016, he moved to Corporate Research in Robert Bosch in Bangalore as a Researcher, where he worked on numerical methods for ordinary differential equations. He joined Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, in December 2017 as a postdoctoral research fellow in the Chair for Software for Systems on Silicon. Farhad is the recipient of the HiPEAC technology transfer award in 2019.

Research Interests

  • Hardware Security
  • Hardware Assisted Security
  • Computer Architecture
  • Performance Modeling
  • Computer Arithmetic

Publications

Publications from May/ 2021 to Dec/ 2017

Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, accepted for publication, ISSN: 1550-4832, 10.1145/3431389


Saxena, V., Reddy, A., Jonathan, N., Gustafson, J. L., Sangeeth, N., Leupers, R. and Merchant, F.: Brightening the Optical Flow through Posit Arithmetic, in International Symposium on Quality Electronic Design (ISQED), Apr. 2021, accepted for publication ©2021 IEEE


Alouani, I., BEN KHALIFA, A., Merchant, F. and Leupers, R.: An Investigation on Inherent Robustness of Posit Data Representation, in Proceedings of the International Conference on VLSI Design (VLSID), Feb. 2021, accepted for publication ©2021 IEEE


Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, accepted for publication


Polian, I., Altmann, F., Arul, T., Boit, C., Brederlaw, R., Davi, L., Drechsler, R., Du, N., Eisenbarth, T., Gü­ney­su, T., Hermann, S., Hiller, M., Leupers, R., Merchant, F., Mussenbrock, T., Katzenbeisser, S., Kumar, A., Kunz, W., Mikolajick, T., Pachauri, V., Seifert, J.-P., Torres, F. S. and Trommer, J.: Nano Security: From Nano-Electronics to Secure Systems, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, accepted for publication


Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, accepted for publication ©2021 IEEE


Guntoro, A., De La Parra, C., Merchant, F., De Dinechin, F., Gustafson, J. L., Langhammer, M., Leupers, R. and Sangeeth, N.: Next Generation Arithmetic for Edge Computing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, 10.23919/DATE48585.2020.9116196 ©2020 IEEE


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, 2020 ©2020 IEEE


VREČA, J. , Sturm, K. J. X., GUNGL, E., Merchant, F., BIENTINESI, P., Leupers, R. and Brezočnik, Z.: Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit, in IEEE Access, 2020, 10.1109/ACCESS.2020.3022824} ©2020 IEEE


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems (SCOPES), p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, 10.1109/VLSID.2019.00092


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019


Šišejković, D., Merchant, F. and Leupers, R.: Protecting the Integrity of Processor Cores with Logic Encryption, in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp. 424-425, 2019, 10.1109/SOCC46988.2019.1570564157 ©2019 IEEE


Chaurasiya, R., John, G., Shrestha, R., Jonathan, N., Sangeeth, N., Kaustav, N., Merchant, F. and Leupers, R.: Parameterized Posit Arithmetic Hardware Generator, in Proceedings of the International Conference on Computer Design (ICCD), pp. 334-341, Oct. 2018, 10.1109/ICCD.2018.00057 ©2018 IEEE


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Achieving Efficient Realization of Kalman Filter on CGRA through Algorithm-Architecture Co-design, in Applied Reconfigurable Computing, May. 2018, 10.1007/978-3-319-78890-6


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Efficient Realization of Householder Transform through Algorithm-Architecture Co-design for Acceleration of QR Factorization, in IEEE Transactions on Parallel and Distributed Systems, IEEE, Mar. 2018, 10.1109/TPDS.2018.2803820 ©2018 IEEE


Merchant, F., Chattopadhyay, A., Raha, S., Nandy, S. K. and Narayan, R.: Accelerating BLAS and LAPACK via Efficient Floating Point Architecture Design, in Parallel Processing Letters, Vol. 27, No. 03n04, World Scientific, pp. 1--17, Dec. 2017, 10.1142/S0129626417500062


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