Publications of Rainer Leupers

Publications from Mar/ 2018 to Oct/ 2016

Buecs, R., Maximilian, F., Leupers, R., Ascheid, G., Stephan, R. and Hoffmann, A.: OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), pp. 281-284, Mar. 2018, ISSN: 1558-1101, 10.23919/DATE.2018.8342020 ©2018 IEEE


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem, in Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) 2018, pp. 59-69, Mar. 2018, 10.5220/0006665900590069


Auras, D., Birke, S., Leupers, R. and Ascheid, G.: Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection, in 2018 Workshop on Computing, Networking and Communications (CNC), Mar. 2018, 10.1109/ICCNC.2018.8390383 ©2018 IEEE


Birke, S., Chen, W.-J., Wang, G., Auras, D., Shen, C.-A., Leupers, R. and Ascheid, G.: VLSI Implementation of Channel Estimation for Millimeter Wave Beamforming Training, in 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS), Feb. 2018, ISBN: 978-1-53862-311-4, 10.1109/LASCAS.2018.8399977 ©2018 IEEE


Führ (Onnebrink), G., Leupers, R. and Ascheid, G.: ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models, in Proceedings of the 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools(Manchester, England), Jan. 2018, 10.1145/3180665.3180667


Lücken, V., Voß, N., Schreier, J., Baag, T., Gehring, M., Raschen, M., Lanius, C., Leupers, R. and Ascheid, G.: Density-Based Statistical Clustering: Enabling Sidefire Ultrasonic Traffic Sensing in Smart Cities, in Journal of Advanced Transportation, Vol. 2018, Wiley-Hindawi, Jan. 2018, 10.1155/2018/9317291


Leupers, R., Aguilar, M. A., Castrillon, J. and Sheng, W.: Software Compilation Techniques for Heterogeneous Embedded Multi-Core Systems, in Handbook of Signal Processing Systems, 2018, 10.1007/978-3-319-91734-4_28


Aguilar, M. A., Eusse, J. F., Ray, P., Leupers, R., Ascheid, G., Sheng, W. and Sharma, P.: Towards Parallelism Extraction for Heterogeneous Multicore Android Devices, in International Journal of Parallel Programming, Vol. 45, No. 6, Springer, pp. 1592-1624, Dec. 2017, ISSN: 1573-7640, 10.1007/s10766-016-0479-5


Aguilar, M. A., Aggarwal, A., Shaheen, A., Leupers, R., Ascheid, G., Castrillon, J. and Fitzpatrick, L.: Multi-Grained Performance Estimation for MPSoC Compilers, in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)(Seoul, Republic of Korea), pp. 14:1-14:2, ACM, Oct. 2017, ISBN: 978-1-45035-184-3, 10.1145/3125501.3125521


Leupers, R., Aguilar, M. A., Eusse, J. F., Castrillon, J. and Sheng, W.: MAPS: A Software Development Environment for Embedded Multicore Applications, in Handbook of Hardware/Software Codesign,Dordrecht, Sep. 2017


Aguilar, M. A., Leupers, R., Ascheid, G. and Eusse, J. F.: Extraction of Recursion Level Parallelism for Embedded Multicore Systems, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2017 ©2017 IEEE


Führ (Onnebrink), G., Walbroel, F., Klimt, J., Leupers, R., Ascheid, G., Murillo, L. G., Schürmans, S., Chen, X. and Harn, Y.: DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Application Mapping, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2017, 10.1109/SAMOS.2017.8344628 ©2017 IEEE


Bytyn, A., Springer, J., Leupers, R. and Ascheid, G.: VLSI implementation of LS-SVM training and classification using entropy based subset-selection, in 2017 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2017, ISBN: 978-1-46736-853-7, 10.1109/ISCAS.2017.8050590 ©2017 IEEE


Aguilar, M. A., Leupers, R., Ascheid, G., Kavvadias, N. and Fitzpatrick, L.: Schedule-Aware Loop Parallelization for Embedded MPSoCs by Exploiting Parallel Slack, in 20th Design Automation and Test in Europe Conference (DATE)(Lausanne, Switzerland), pp. 1237-1240 , European Design and Automation Association, Mar. 2017, 10.23919/DATE.2017.7927178 ©2017 IEEE


Weinstock, J. H., Leupers, R. and Ascheid, G.: Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models, in Proceedings of the 2017 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools(Stockholm, Sweden), Jan. 2017, ISBN: 978-1-45034-840-9, 10.1145/3023973.3023975


Auras-Rodriguez, M. H., Zimmermann, A., Ascheid, G. and Leupers, R.: Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition, in Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms(New York, NY, USA), pp. 13--18, ACM, 2017, ISBN: 978-1-45034-877-5, 10.1145/3029580.3029583


Buecs, R., Reyes Aristizabal, J. S., Leupers, R. and Ascheid, G.: Multi-Level Vehicle Dynamics Modeling and Export for ADAS Prototyping in a 3D Driving Environment, in ITSC, pp. 1980-1987, 2017, ISBN: 978-1-53861-525-6, ISSN: 2153-0017 ©2017 IEEE


Schürmans, S., Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Chen, X.: Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model, in (ACM TECS), Vol. 16, No. 1, ACM, pp. 26:1--26:26, Oct. 2016, ISSN: 1539-9087, 10.1145/2987375


Murillo, L. G., Buecs, R., Leupers, R. and Ascheid, G.: MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs, in (ACM TECS), Vol. 16, No. 1, ACM, pp. 7:1--7:25, Oct. 2016, ISSN: 1539-9087, 10.1145/2950052


Auras, D., Birke, S., Piwczyk, T., Leupers, R. and Ascheid, G.: A Flexible MCMC Detector ASIC, in Proceedings of the 2016 International SoC Design Conference (ISOCC), Oct. 2016, ISBN: 978-1-50903-219-8, 10.1109/ISOCC.2016.7799789 ©2016 IEEE


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