Publications of Rainer Leupers

Publications from Apr/ 2021 to Nov/ 2019

Saxena, V., Reddy, A., Jonathan, N., Gustafson, J. L., Sangeeth, N., Leupers, R. and Merchant, F.: Brightening the Optical Flow through Posit Arithmetic, in International Symposium on Quality Electronic Design (ISQED), Apr. 2021, accepted for publication ©2021 IEEE


Alouani, I., BEN KHALIFA, A., Merchant, F. and Leupers, R.: An Investigation on Inherent Robustness of Posit Data Representation, in Proceedings of the International Conference on VLSI Design (VLSID), Feb. 2021, accepted for publication ©2021 IEEE


Jünger, L., Bianco, C., Niederholtmeyer, K., Petras, D. and Leupers, R.: Optimizing Temporal Decoupling using Event Relevance, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, accepted for publication


Polian, I., Altmann, F., Arul, T., Boit, C., Brederlaw, R., Davi, L., Drechsler, R., Du, N., Eisenbarth, T., Gü­ney­su, T., Hermann, S., Hiller, M., Leupers, R., Merchant, F., Mussenbrock, T., Katzenbeisser, S., Kumar, A., Kunz, W., Mikolajick, T., Pachauri, V., Seifert, J.-P., Torres, F. S. and Trommer, J.: Nano Security: From Nano-Electronics to Secure Systems, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, accepted for publication


Joseph, J. M., Bamberg, L., Geonhwa, J., Chien, R.-T., Leupers, R., García-Ortiz, A., Krishna, T. and Pionteck, T.: Bridging the F requency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, accepted for publication, 10.1145/3394885.3431421


Joseph, J. M., Samajdar, A., Zhu, L., Leupers, R., Lim, S.-K., Pionteck, T. and Krishna, T.: Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators, in International Symposium on Quality Electronic Design (ISQED), 2021, accepted for publication


Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, accepted for publication ©2021 IEEE


Copic, M., Leupers, R. and Ascheid, G.: Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables, in Proceedings of 31st International Symposium on Software Reliability Engineering (ISSRE), pp. 127-137, Oct. 2020, 10.1109/ISSRE5003.2020.00021 ©2020 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, ISBN: 978-3-03052-794-5, 10.1007/978-3-030-52794-5_5


Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004


Führ (Onnebrink), G., Aramburú, J., Leupers, R. and Eusse, J. F.: Memory Power-Performance Trade-Off based on SW Task Mapping and Graph Transformation, in The Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores, Jan. 2020


Jünger, L., Bölke, J., Tobies, S., Hoffmann, A. and Leupers, R.: ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020 ©2020 IEEE


Guntoro, A., De La Parra, C., Merchant, F., De Dinechin, F., Gustafson, J. L., Langhammer, M., Leupers, R. and Sangeeth, N.: Next Generation Arithmetic for Edge Computing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, 10.23919/DATE48585.2020.9116196 ©2020 IEEE


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, 2020 ©2020 IEEE


VREČA, J. , Sturm, K. J. X., GUNGL, E., Merchant, F., BIENTINESI, P., Leupers, R. and Brezočnik, Z.: Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit, in IEEE Access, 2020, 10.1109/ACCESS.2020.3022824} ©2020 IEEE


Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), ACM, p. 25, 2020, accepted for publication


Jünger, L., Zurstraßen, N., Kogel, T., Keding, H. and Leupers, R.: AMAIX: A Generic Analytical Model for Deep Learning Accelerators, in SAMOS International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, pp. 36-51, Springer, 2020, 10.1007/978-3-030-60939-9_3


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems (SCOPES), p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005


Strobel, M., Führ (Onnebrink), G., Radetzki, M. and Leupers, R.: Combined MPSoC Task Mapping and Memory Optimization for Low-Power, in IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)(Bangkok, Thailand), pp. 121-124, Nov. 2019, 10.1109/APCCAS47518.2019.8953133 ©2019 IEEE


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