Publications of Rainer Leupers

Publications from May/ 2019 to Mar/ 2018

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2019


Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC), Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE


Schürmans, S. and Leupers, R.: Power Estimation on Electronic System Level using Linear Power Models, Springer International Publishing, 1 ed., Feb. 2019, ISBN: 978-3-03001-875-7, 10.1007/978-3-030-01875-7


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Feb. 2019, accepted for publication, 10.1109/LES.2019.2901224


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, accepted for publication


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, accepted for publication


Copic, M., Leupers, R. and Ascheid, G.: Efficient Sporadic Task Handling in Parallel AUTOSAR Applications Using Runnable Migration, in 24th Asia and South Pacific Design Automation Conference (ASP-DAC 2019), Jan. 2019, accepted for publication


Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, 2019, accepted for publication


Buecs, R., Leupers, R. and Ascheid, G.: Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping, in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Oct. 2018 ©2018 IEEE


Bhattacharyya, S., Deprettere, E., Leupers, R. and Takala, J.: Handbook of Signal Processing Systems, Springer, 3rd ed., Oct. 2018, ISBN: 978-1-44196-344-4, 10.1007/978-3-319-91734-4


Buecs, R., Marcel, H., Leupers, R. and Ascheid, G.: Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach, in 2018 IEEE International Conference on Vehicular Electronics and Safety (ICVES), Sep. 2018, 10.1109/ICVES.2018.8519593 ©2018 IEEE


Weinstock, J. H., Buecs, R., Walbroel, F., Leupers, R. and Ascheid, G.: AMVP - a high performance virtual platform using parallel SystemC for multicore ARM architectures: work-in-progress, in International Conference on Hardware/Software Codesign and System Synthesis (CODES)(Piscataway, NJ, USA), pp. 13:1--13:2, IEEE Press, Sep. 2018, ISBN: 978-1-53865-562-7


Šišejković, D., Leupers, R., Ascheid, G. and Metzner, S.: A Unifying Logic Encryption Security Metric, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2018, 10.1145/3229631.3229636


Buecs, R., Maximilian, F., Leupers, R., Ascheid, G., Stephan, R. and Hoffmann, A.: OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), pp. 281-284, Mar. 2018, ISSN: 1558-1101, 10.23919/DATE.2018.8342020 ©2018 IEEE


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem, in Proceedings of the 4th International Conference on Vehicle Technology and Intelligent Transport Systems (VEHITS) 2018, pp. 59-69, Mar. 2018, 10.5220/0006665900590069


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