Publications of Rainer Leupers

Publications from Oct/ 2021 to Jan/ 2020

Reimann, L. M., Hanel, L., Šišejković, D., Merchant, F. and Leupers, R.: QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog, in Proceedings of the International Conference on Computer Design (ICCD), Oct. 2021, accepted for publication ©2021 IEEE


Staudigl, F., Merchant, F. and Leupers, R.: A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators and Security, in IEEE Design & Test, Sep. 2021, accepted for publication ©2021 IEEE


Šišejković, D., Merchant, F., Reimann, L. M. and Leupers, R.: Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Jul. 2021, ISSN: 1937-4151, 10.1109/TCAD.2021.3100275 ©2021 IEEE


Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, ISSN: 1550-4832, 10.1145/3431389


Saxena, V., Reddy, A., Jonathan, N., Gustafson, J. L., Sangeeth, N., Leupers, R. and Merchant, F.: Brightening the Optical Flow through Posit Arithmetic, in International Symposium on Quality Electronic Design (ISQED), Apr. 2021, 10.1109/ISQED51717.2021.9424360 ©2021 IEEE


Alouani, I., BEN KHALIFA, A., Merchant, F. and Leupers, R.: An Investigation on Inherent Robustness of Posit Data Representation, in Proceedings of the International Conference on VLSI Design (VLSID), Feb. 2021, 10.1109/VLSID51830.2021.00052 ©2021 IEEE


Jünger, L., Bianco, C., Niederholtmeyer, K., Petras, D. and Leupers, R.: Optimizing Temporal Decoupling using Event Relevance, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, 10.1145/3394885.3431419


Polian, I., Altmann, F., Arul, T., Boit, C., Brederlaw, R., Davi, L., Drechsler, R., Du, N., Eisenbarth, T., Gü­ney­su, T., Hermann, S., Hiller, M., Leupers, R., Merchant, F., Mussenbrock, T., Katzenbeisser, S., Kumar, A., Kunz, W., Mikolajick, T., Pachauri, V., Seifert, J.-P., Torres, F. S. and Trommer, J.: Nano Security: From Nano-Electronics to Secure Systems, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, 10.23919/DATE51398.2021.9474187


Joseph, J. M., Bamberg, L., Geonhwa, J., Chien, R.-T., Leupers, R., García-Ortiz, A., Krishna, T. and Pionteck, T.: Bridging the F requency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), 2021, 10.1145/3394885.3431421


Joseph, J. M., Samajdar, A., Zhu, L., Leupers, R., Lim, S.-K., Pionteck, T. and Krishna, T.: Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators, in International Symposium on Quality Electronic Design (ISQED), 2021, accepted for publication


Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, 10.1109/VLSID51830.2021.00051 ©2021 IEEE


Šišejković, D., Reimann, L. M., Moussavi, E., Merchant, F. and Leupers, R.: Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), 2021, accepted for publication ©2021 IEEE


Šišejković, D. and Leupers, R.: Trustworthy Hardware Design with Logic Locking, in IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SOC), IEEE, 2021, accepted for publication ©2021 IEEE


Copic, M., Leupers, R. and Ascheid, G.: Leveraging Nondeterminism in Mixed Classic/Adaptive AUTOSAR Systems for Runnable Configuration, in Design Automation Conference (DAC), Work-in-Progress Session, 2021, accepted for publication


Copic, M., Leupers, R. and Ascheid, G.: Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism, in Proceedings of 24th Euromicro Conference on Digital System Design (DSD), 2021, accepted for publication


Galicia, M., BanaGozar, A., Sturm, K. J. X., Staudigl, F., Stuijk, S., Corporaal, H. and Leupers, R.: NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators, in International Conference on Communications and Technology, IEEE SOCC, 2021, accepted for publication ©2021 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNN, in IEEE Open Journal of Circuits and Systems, Vol. 2, pp. 3-15, 2021, 10.1109/OJCAS.2020.3037758


Copic, M., Leupers, R. and Ascheid, G.: Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables, in Proceedings of 31st International Symposium on Software Reliability Engineering (ISSRE), pp. 127-137, Oct. 2020, 10.1109/ISSRE5003.2020.00021 ©2020 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, ISBN: 978-3-03052-794-5, 10.1007/978-3-030-52794-5_5


Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004


>>