Publications of Rainer Leupers

Publications from Jan/ 2020 to Oct/ 2018

Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004


Jünger, L., Bölke, J., Tobies, S., Hoffmann, A. and Leupers, R.: ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, accepted for publication ©2020 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005


Strobel, M., Führ (Onnebrink), G., Radetzki, M. and Leupers, R.: Combined MPSoC Task Mapping and Memory Optimization for Low-Power, in IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)(Bangkok, Thailand), Nov. 2019 ©2019 IEEE


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, Vol. 992, Springer, pp. 181-201, Mar. 2019, 10.1007/978-3-030-26633-2_9


Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC), Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE


Schürmans, S. and Leupers, R.: Power Estimation on Electronic System Level using Linear Power Models, Springer International Publishing, 1 ed., Feb. 2019, ISBN: 978-3-03001-875-7, 10.1007/978-3-030-01875-7


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, accepted for publication, 10.1109/VLSID.2019.00092


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-design, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019


Copic, M., Leupers, R. and Ascheid, G.: Efficient Sporadic Task Handling in Parallel AUTOSAR Applications Using Runnable Migration, in Proceedings of the 24th Asia and South Pacific Design Automation Conference(New York, NY, USA), pp. 603-608 , ACM, Jan. 2019, ISBN: 978-1-45036-007-4, 10.1145/3287624.3287654


Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191


Chaurasiya, R., John, G., Shrestha, R., Jonathan, N., Sangeeth, N., Kaustav, N., Merchant, F. and Leupers, R.: Parameterized Posit Arithmetic Hardware Generator, in Proceedings of the International Conference on Computer Design (ICCD), pp. 334-341, Oct. 2018, 10.1109/ICCD.2018.00057 ©2018 IEEE


Buecs, R., Leupers, R. and Ascheid, G.: Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping, in 2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 532-535, IEEE, Oct. 2018, 10.1109/APCCAS.2018.8605685 ©2018 IEEE


Bhattacharyya, S., Deprettere, E., Leupers, R. and Takala, J.: Handbook of Signal Processing Systems, Springer International Publishing, 3rd ed., Oct. 2018, ISBN: 978-3-31991-733-7, 10.1007/978-3-319-91734-4


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