Publications of Rainer Leupers

Publications from Mar/ 2020 to Jan/ 2019

Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: 3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs, in ARCS - International Conference on Architecture of Computing Systems, Mar. 2020, accepted for publication


Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004


Führ (Onnebrink), G., Aramburú, J., Leupers, R. and Eusse, J. F.: Memory Power-Performance Trade-Off based on SW Task Mapping and Graph Transformation, in The Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores, Jan. 2020


Jünger, L., Bölke, J., Tobies, S., Hoffmann, A. and Leupers, R.: ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, accepted for publication ©2020 IEEE


Guntoro, A., De La Parra, C., Merchant, F., De Dinechin, F., Gustafson, J. L., Langhammer, M., Leupers, R. and Sangeeth, N.: Next Generation Arithmetic for Edge Computing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2020, accepted for publication


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems -- ARCS 2020, Springer International Publishing, 2020, accepted for publication ©2020 IEEE


Jünger, L., Zurstraßen, N., Kogel, T., Keding, H. and Leupers, R.: AMAIX: A Generic Analytical Model for Deep Learning Accelerators, in SAMOS International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2020, accepted for publication


Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems, p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005


Strobel, M., Führ (Onnebrink), G., Radetzki, M. and Leupers, R.: Combined MPSoC Task Mapping and Memory Optimization for Low-Power, in IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)(Bangkok, Thailand), pp. 121-124, Nov. 2019, 10.1109/APCCAS47518.2019.8953133 ©2019 IEEE


Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE


Bytyn, A., Leupers, R. and Ascheid, G.: An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, May. 2019, ISBN: 978-1-72810-397-6, 10.1109/ISCAS.2019.8702357


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE


Buecs, R., Pramod, L., Weinstock, J. H., Walbroel, F., Leupers, R. and Ascheid, G.: A Multi-Domain Co-Simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping, in Smart Cities, Green Technologies, and Intelligent Transport Systems: 4th International Conference, SMARTGREENS 2015, and 1st International Conference VEHITS 2018, Revised Selected Papers, Vol. 992, Springer, pp. 181-201, Mar. 2019, 10.1007/978-3-030-26633-2_9


Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC), Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE


Schürmans, S. and Leupers, R.: Power Estimation on Electronic System Level using Linear Power Models, Springer International Publishing, 1 ed., Feb. 2019, ISBN: 978-3-03001-875-7, 10.1007/978-3-030-01875-7


Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Shaheen, A.: A Heuristic for Multi Objective Software Application Mappings on Heterogeneous MPSoCs, in Proceedings of the Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2019, 10.1145/3287624.3287651


Merchant, F., Vatwani, T., Chattopadhyay, A., Raha, S., Nandy, S. K., Narayan, R. and Leupers, R.: Applying Modified Householder Transform to Kalman Filter, in Proceedings of the International Conference on VLSI Design (VLSID), Jan. 2019, 10.1109/VLSID.2019.00092


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