Dominik Šišejković


Thesis & Student Jobs

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Dominik Šišejković received the B.Sc. and M.Sc. degree in computing (software engineering and information systems) from the Faculty of Electrical Engineering and Computing, University of Zagreb, Croatia, in 2014 and 2016 respectively. In September 2016, he started working as a Ph.D. student and research assistant at the Institute for Communication Technologies and Embedded Systems. Since September 2017, he is working as the Technical Project Officer of the EU-funded project TETRAMAX; facilitating technology transfer from academia to European SMEs. From October 2018, he is the Chief Engineer of the Chair for Software for Systems on Silicon. In addition, he was directly involved in the design and implementation of the logic locking framework that was applied for the production of the first logic locked RISC-V processor core on the market. Since 2019, he co-organizes the annual SeHAS workshop on secure hardware, architectures and operating systems at the HiPEAC conference. Since 2020, he is part of the technical committee for the hardware and systems security track at the International Symposium on Quality Electronic Design (ISQED). He received the ICT Young Researcher Award 2020 by RWTH Aachen University for significant contributions in the ICT research area. Moreover, he was awarded the HiPEAC Technology Transfer Award 2020 for successfully transferring a scalable logic locking framework for hardware integrity protection to industry. Since 2020, he is an ACM professional member. 

Research Interest

  • Hardware Security
  • Secure Processor Design
  • Embedded Systems
  • Machine Learning for Security


Šišejković, D., Merchant, F., Reimann, L. M., Srivastava, H., Hallawa, A. and Leupers, R.: Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach, in ACM Journal on Emerging Technologies in Computing Systems (JETC), Vol. 17, No. 3, Association for Computing Machinery, p. 26, May. 2021, accepted for publication, ISSN: 1550-4832, 10.1145/3431389

Rai, S., Garg, S., Pilato, C., Herdt, V., Moussavi, E., Šišejković, D., Karri, R., Drechsler, R., Merchant, F. and Kumar, A.: Vertical IP Protection of the Next-Generation Devices: Quo Vadis?, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), IEEE, 2021, accepted for publication

Merchant, F., Šišejković, D., Reimann, L. M., Yasotharan, K., Grass, T. and Leupers, R.: ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework, in Proceedings of the International Conference on VLSI Design (VLSID), 2021, accepted for publication ©2021 IEEE

Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R. and Kegreiß, S.: Scaling Logic Locking Schemes to Multi-Module Hardware Designs, in Architecture of Computing Systems (ARCS 2020), Springer International Publishing, 2020 ©2020 IEEE

Šišejković, D., Merchant, F., Reimann, L. M., Leupers, R., Giacometti, M. and Kegreiß, S.: A Secure Hardware-Software Solution Based on RISC-V, Logic Locking and Microkernel, in Proceedings of the 23nd International Workshop on Software and Compilers for Embedded Systems (SCOPES), p. 62–65, Association for Computing Machinery, 2020, 10.1145/3378678.3391886 ©2020 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 2019 IEEE European Test Symposium (ETS), pp. 1-6, May. 2019, ISSN: 1530-1877, 10.1109/ETS.2019.8791528 ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiß, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), IEEE, p. 4, Apr. 2019, 10.1109/VLSI-DAT.2019.8741531 ©2019 IEEE

Šišejković, D., Merchant, F. and Leupers, R.: Protecting the Integrity of Processor Cores with Logic Encryption, in 2019 32nd IEEE International System-on-Chip Conference (SOCC), pp. 424-425, 2019, 10.1109/SOCC46988.2019.1570564157 ©2019 IEEE

Đumić, M., Šišejković, D., Čorić , R. and Jakobović, D.: Evolving Priority Rules for the Resource Constrained Project Scheduling Problem with Genetic Programming, in Future Generation Computer Systems, Vol. 86, pp. 211 - 221, Sep. 2018, ISSN: 0167-739X, 10.1016/j.future.2018.04.029

Šišejković, D., Leupers, R., Ascheid, G. and Metzner, S.: A Unifying Logic Encryption Security Metric, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), ACM, Jul. 2018, 10.1145/3229631.3229636

Picek, S., Šišejković, D. and Jakobović, D.: Immunological Algorithms Paradigm for Construction of Boolean Functions with Good Cryptographic Properties, in Engineering Applications of Artificial Intelligence, Vol. 62, pp. 320 - 330, Jun. 2017, ISSN: 0952-1976, 10.1016/j.engappai.2016.11.002

Picek, S., Šišejković, D., Jakobović, D., Batina, L., Yang, B., Sijacic, D. and Mentens, N.: Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware, in International Conference on Cryptology in Africa (AFRICACRYPT), ACM, pp. 147-166, Apr. 2016, 10.1007/978-3-319-31517-1_8

Picek, S., Šišejković, D., Rozic, V., Yang, B., Jakobović, D. and Mentens, N.: Evolving Cryptographic Pseudorandom Number Generators, in Parallel Problem Solving from Nature (PPSN), Springer International Publishing, pp. 613--622, 2016, 978-3-319-45823-6_57

Batina, L., Jakobović, D., Picek, S., de la Piedra, A. and Šišejković, D.: S-box Pipelining Using Genetic Algorithms for High-Throughput AES Implementations: How Fast Can We Go?, in International Conference on Cryptology in India (Indocrypt), Springer International Publishing, pp. 322--337, 2014, 10.1007/978-3-319-13039-2_19