Chair for Software for Systems on Silicon

  • RWTH Aachen University is Germany´s top-ranked technical university with approx. 45,000 students. The Institute for Communication Technologies and Embedded Systems (ICE) is headed by Prof. Rainer Leupers and Prof. Dr. Haris Gačanin. ICE performs R&D projects in different areas of embedded and cyber-physical system design. Our main application domains are mobile communications, automotive…

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Chair for Distributed Signal Processing

HiWi / WiHi job offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • Hardware Security: Secure Processor Design

    Supervisor: Lennart Reimann
    Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

  • HiWi/WiHi jobs for Summer 2021

    Supervisor: Dr. Haris Kremo
    Description: Chair for Distributed Signal Processing offers multiple HiWi positions to develop laboratory exercises for the course titled Signal Processing for Mobile Communications: Extended Transceiver Design. The course treats parts of the transmitter-receiver chain beyond simple signal transmission and detection covered in an earlier course. The topics include synchronization, channel estimation, error correction coding, etc. The positions are offered for preferably MS students in the Summer 2021 semester.

  • HW Tracing and Measurement System for the Validation of ReRAM PIM Models

    Supervisor: José Cubero
    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are developing models and simulation tools to enable the architectural exploration of novel memristor-based PIM solutions. To validate and calibrate our models, a comparison against real HW prototypes is of utmost importance. The goal of this project is to create a custom measuring system for this purpose, consisting of current sensing devices, ADCs and an MCU.

  • Machine Learning for Security

    Supervisor: Dominik Šišejković
    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • Neuromorphic Hardware Security

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to investigate novel Hardware Security vulnerabilities and their countermeasure of neuromorphic computing architecture. In particular, the student will have the unique opportunity to work with the real ReRAM crossbars to perform measurements within our labs.

  • Neuromorphic Virtual Platforms

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to develop a virtual prototype to perform a system exploration concerning parameters like power consumption and performance. The virtual prototype will be implemented in C++ together with SystemC/TLM.

  • NoC design-space exploration for neuromorphic massive multicore systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to model NoCs with a fast and abstract performance model. The model shall cover the state of routers in slices of time. Input bandwidth, output bandwidth and network latency must be estimated.

  • RISCV plus TensorFlowLite Hardware Platform

    Supervisor: PhD-Ing. Melvin Galicia
    Description: RISCV processors have gained a good level of maturity in the academia and they are trying to breakthrough in the industry. Attaching  RISCV processors to booming commercial technologies like maching learning software is a very promising idea. The job is to bring to life a realization of a platform, where TensorFlow-Lite framework can be compiled and run in an actual RISCV processor.

  • We are hiring! Programmers (C++, Python), Data Scientists, Hardware Engineers

    Supervisor: Dr. Jan Moritz Joseph
    Description: There is plenty of work in our team. Developing hardware, building prototypes, maintaining open-source software, or inventing new ML models? That’s all possible! We will find a task that fits your profile best.

  • Wi-Hi Position: Programming

    Tutor: Shawan Mohammed
    Description: The ICE is looking for a Bachelor graduate who will be employed for software development as a half-time scientific assistant (WiHi, 20h per week).

Research Assistants / Ph.D. students positions in 6G wireless communications

We have open vacancies for research assistants / Ph.D. students at the Institute for Communication Technologies and Embedded Systems ( of RWTH Aachen University with Univ.-Prof. Haris Gačanin.

Who we are:

The ICE ( performs R&D projects in different areas of communications, embedded, and cyber-physical system design. Our main application domains are next-generation wireless communications, automotive electronics, cyber-security, and Industry 4.0. ICE maintains tight cooperation with industry partners worldwide and has transferred numerous technologies to semiconductor vendors, system houses, and EDA companies.

This position is a part of the development of a novel physical-layer design for low-latency applications including following topics, device-to-device communications, multi-antenna systems, channel estimation, adaptive equalization, radio resource management, beamforming, radar/sensing-communications. We are looking for researchers who can develop concepts and prototype new communication ideas. The successful candidates will have extensive career development and mentoring opportunities. The researchers will present their work internally and externally, to technical and non-technical audiences. It is highly expected to publish research results in top-quality IEEE journals and conferences.


  1. Contribute to R&D projects through the development of simulators and prototypes
  2. Participate in collaboration projects with our academic and industry partners
  3. Support event organization and assist in teaching, e.g. lecture exercises, labs, and seminars


  1. Applicants must hold a Master of Science in electrical engineering or computer science equivalent and compliant to RWTH Aachen requirements for a Ph.D.
  2. The candidates must have excellent knowledge of radio/wireless communications, probability theory, and linear algebra with applications in signal processing. Evidence of projects applying machine learning is a plus.
    1. Extensive knowledge in C/C++ and Linux. List the evidence in the form of past projects.
    2. extensive hands-on experience with at least one of the SDR platforms and FPGA programming. List the evidence in the form of past projects.
  3. It is expected that missing skills will be proactively improved.
  4. The candidates must have excellent team player spirit and communication skills while being able to work independently. Mandatory is a high proficiency in oral and written English.

We offer:

Full-time employment with TVL-13 salary level. No tuition fees for Ph.D. studies.

Your application must include:

  1. A research statement (max 1 page) indicating the candidate’s research interests, achievements, plans, and how these fit with the above position requirements and our ongoing research.
  2. Brief description of projects in C/C++/SDRs/FPGA.
  3. Curriculum vitae (e.g., publications, R&D skills, awards, fellowships, grants).
  4. Copies of BSc and MSc degrees (or date of expected graduation), an official transcript of the completed subjects with GPA
  5. Names of at least two references


How to apply?

Send the required documents in the order a) - e) within a single pdf file

Subject: PhD-Jobs-DSP-RWTH-Name_SURNAME

Apply/Questions: jobs-dsp(at)