Tools Research (SSS)

  • RWTH Aachen University is Germany´s top-ranked technical university with approx. 45,000 students. The Institute for Communication Technologies and Embedded Systems (ICE) is headed by Prof. Rainer Leupers and Prof. Gerd Ascheid. ICE performs R&D projects in different areas of embedded and cyber-physical system design. Our main application domains are mobile communications, automotive electronics,…

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HiWi / WiHi job offers

Hardware-Security: Secure Processor Design:


Dominik Šišejković


Depending on the actual task, the following is essential:

  • Good programming skills in C++ (object-oriented programming)
  • Experience with Python (can be learned in a short time)
  • Linux OS
  • Basic understanding of the hardware design and fabrication flow
  • Some experience with computer architecture
  • Some experience with Verilog
Nice to have:
  • Experience with the Synopsys Design Compiler
  • Experience with ModelSim from Mentor
A background on hardware security is not necessary, but appreciated. In case of interest, please send me an email including the following:
  • Latest transcript of records
  • A brief description of your background and motivation
  • CV (if available)


Nowadays, it has become a major challenge to secure a hardware design from being tampered with while in the hands of external design houses or in the fabrication. These malicious modifications imposed by external parties are known as hardware Trojans. Trojans can lead to serious repercussions, including data leakage, denial of service attacks and others.


Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.


We are looking into several aspects of securing a processor design. Some example tasks are as follows:

  • Implementation of novel logic encryption algorithms
  • Exploring new methodologies to secure processor designs
  • Desing of hardware Trojans
  • Evaluation of existing methodologies in terms of area/delay/power vs. security for hardware models of processor cores
  • Hardware security metrics
More information can be found here.