Jobs

Chair for Software for Systems on Silicon

  • RWTH Aachen University is Germany´s top-ranked technical university with approx. 45,000 students. The Institute for Communication Technologies and Embedded Systems (ICE) is headed by Prof. Rainer Leupers and Prof. Dr. Haris Gačanin. ICE performs R&D projects in different areas of embedded and cyber-physical system design. Our main application domains are mobile communications, automotive…

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Chair for Distributed Signal Processing

  • There are different opportunities for excellent postdoctoral researchers, which are hired and compensated as full-time researchers, at the Chair for Distributed Signal Processing (Prof. Dr. Haris Gačanin, www.dsp.rwth-aachen.de) of RWTH Aachen University in Aachen, Germany. Current positions are part of efforts toward the development of 6G radio access technologies and laboratory in the…

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  • There are multiple vacancies for excellent Ph.D. candidates, which are hired and compensated as full-time researchers, at the Chair for Distributed Signal Processing (Prof. Dr. Haris Gačanin, www.dsp.rwth-aachen.de) of RWTH Aachen University in Aachen, Germany. Current positions are part of efforts toward the development of 6G radio access technologies and laboratory in the intersection of digital…

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HiWi / WiHi job offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • Hardware Security: Secure Processor Design

    Supervisor: Lennart Reimann
    Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

  • HiWi/WiHi jobs for Summer 2021

    Supervisor: Dr. Haris Kremo
    Description: Chair for Distributed Signal Processing offers multiple HiWi positions to develop laboratory exercises for the course titled Signal Processing for Mobile Communications: Extended Transceiver Design. The course treats parts of the transmitter-receiver chain beyond simple signal transmission and detection covered in an earlier course. The topics include synchronization, channel estimation, error correction coding, etc. The positions are offered for preferably MS students in the Summer 2021 semester.

  • Machine Learning for Security

    Supervisor: Dominik Šišejković
    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • Neuromorphic Hardware Security

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to investigate novel Hardware Security vulnerabilities and their countermeasure of neuromorphic computing architecture. In particular, the student will have the unique opportunity to work with the real ReRAM crossbars to perform measurements within our labs.

  • Neuromorphic Virtual Platforms

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to develop a virtual prototype to perform a system exploration concerning parameters like power consumption and performance. The virtual prototype will be implemented in C++ together with SystemC/TLM.

  • NoC design-space exploration for neuromorphic massive multicore systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to model NoCs with a fast and abstract performance model. The model shall cover the state of routers in slices of time. Input bandwidth, output bandwidth and network latency must be estimated.

  • RISCV plus TensorFlowLite Hardware Platform

    Supervisor: PhD-Ing. Melvin Galicia
    Description: RISCV processors have gained a good level of maturity in the academia and they are trying to breakthrough in the industry. Attaching  RISCV processors to booming commercial technologies like maching learning software is a very promising idea. The job is to bring to life a realization of a platform, where TensorFlow-Lite framework can be compiled and run in an actual RISCV processor.

  • We are hiring! Programmers (C++, Python), Data Scientists, Hardware Engineers

    Supervisor: Dr. Jan Moritz Joseph
    Description: There is plenty of work in our team. Developing hardware, building prototypes, maintaining open-source software, or inventing new ML models? That’s all possible! We will find a task that fits your profile best.

  • Wi-Hi Position: Programming

    Tutor: Shawan Mohammed
    Description: The ICE is looking for a Bachelor graduate who will be employed for software development as a half-time scientific assistant (WiHi, 20h per week).

Hardware Security: Secure Processor Design:

Supervisor:

Lennart Reimann

Requirements:

Depending on the task the following is essential:

  • Experience in object-oriented programming (python or C++)
  • Linux OS
  • Basic understanding of the hardware design and fabrication flow
  • Basic understanding of processor architectures
  • Some experience with Verilog and/or VHDL
In case of interest, please email me and include the following:
  • Latest transcript of records
  • A brief description of your background and motivation
  • CV

Background:

The integrity and security of the hardware was taken for granted for quite some time. In the last years, more and more security problems in commercial hardware were made public, such as Meltdown and Spectre in certain processors. Nowadays a lot of research focuses on the topic of Hardware Security. Securing hardware and removing vulnerability issues before they are manufactured. A pretty interesting approach of achieving this are static analyses of the hardware architecture to assure certain security features.

Description:

In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

Tasks:

We are looking in to guarantee the four security features (CIAA) mentioned above for a processor design. Some example tasks are as follows:

  • Researching state-of-the-art approaches
  • Developing software tools to generate abstract models of the processor
  • Researching vulnerabilities of processor architectures
  • Developing schemes to elaborate the processor of those vulnerabilities
  • Developing a software tool to identify vulnerabilities and quantify them
More Information can be found here: Project Harware Security - Secure processor design.