Jobs

HiWi / WiHi job offers

• Abstract TLM-based Model for on-Chip Interconnects

  Supervisor: Dr.-Ing. Jan Moritz Joseph
  Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.
  
  

• Hardware-Security: IP Integrity Protection

  Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
  Supervisor: Dominik Šišejković
  
  

• Hardware Security: Secure Processor Design

  Supervisor: Lennart Reimann
  Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.
  
  

• High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

  Supervisor: Dr.-Ing. Jan Moritz Joseph
  Description: The goal of this thesis is to extend a the aforementioned framework by a new in-house NoC model. Furthermore, a experiemental setup to assess the NoC's side channels must be implemented (including measurements in the lab).
  
  

• HiWi job offer - Pluto and webportal exercise

  Description: We introduce an interactive learning portal to complement teaching with combination of software and hardware exercises. We defined computer simulation exercises and educational software-defined radio (SDR) platform where baseband functions are implemented in SDR to experience a real-life communication over a wireless channel. The simulations and the hands-on exercises seamlessly merge through reuse of essentially the same C language-based code. The major goals are as follows:
  • Provide interactive web-based platform for the students to remotely, at time of their choice, and with maximum flexibility in execution simulate theoretic concepts covered in class.
  • Provide state-of-the-art hands-on experience to the students with the specified software defined radio. Students can implement, try, and manipulate the code running on the software radio to develop deep understanding of the theoretic concepts learned in class.
  
  Supervisor: Dr. H. Kremo
  
  

• Machine Learning for Security

  Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.
  Supervisor: Dominik Šišejković
  
  

• Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

  Supervisor: Felix Staudigl
  Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.
  
  

• Neuromorphic Hardware Security

  Supervisor: Felix Staudigl
  Description: This Master/Bachelor Thesis aims to investigate novel Hardware Security vulnerabilities and their countermeasure of neuromorphic computing architecture. In particular, the student will have the unique opportunity to work with the real ReRAM crossbars to perform measurements within our labs.
  
  

• Neuromorphic Virtual Platforms

  Supervisor: Felix Staudigl
  Description: This Master/Bachelor Thesis aims to develop a virtual prototype to perform a system exploration concerning parameters like power consumption and performance. The virtual prototype will be implemented in C++ together with SystemC/TLM.
  
  

• RISCV plus TensorFlowLite Hardware Platform

  Supervisor: PhD-Ing. Melvin Galicia
  Description: RISCV processors have gained a good level of maturity in the academia and they are trying to breakthrough in the industry. Attaching  RISCV processors to booming commercial technologies like maching learning software is a very promising idea. The job is to bring to life a realization of a platform, where TensorFlow-Lite framework can be compiled and run in an actual RISCV processor.
  
  

• Tackling Avalanches in Spiking Neural Network Accelerators

  Description: In this master thesis, a standard spiking neural network is trained using Tensorflow. The avalanches are shown by means of software. Next, the amount and timing of avalanches are modeled mathematically. Furthermore, the software model is attached to a SystemC model of the on-chip network. The performance impact of avalanches is quantified. Finally, an architectural optimization is proposed to overcome performance limitations. 
  Supervisor: Dr.-Ing. Jan Moritz Joseph
  
  

• We are hiring! Programmers (C++, Python), Data Scientists, Hardware Engineers

  Description: There is plenty of work in our team. Developing hardware, building prototypes, maintaining open-source software, or inventing new ML models? That’s all possible! We will find a task that fits your profile best.
  
  

• Wi-Hi Position: Programming

  Description: The ICE is looking for a Bachelor graduate who will be employed for software development as a half-time scientific assistant (WiHi, 20h per week).
  Tutor: Shawan Mohammed