Publications of Juan Fernando Eusse ( Alumni Assistant )
- Towards Parallelism Extraction for Heterogeneous Multicore Android Devices, International Journal of Parallel Programming, vol. 45, pp. 1592–1624, Dec. 2017, 10.1007/s10766-016-0479-5.
- MAPS: A Software Development Environment for Embedded Multicore Applications, in Handbook of Hardware/Software Codesign Dordrecht: Springer Netherlands, Sept. 2017.
– doi: 10.1007/978-94-017-7358-4_2-1 –.
- Extraction of Recursion Level Parallelism for Embedded Multicore Systems, in International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) July 2017, ©2017 IEEE.
- Concurrent Memory Subsystem and Application Optimization for ASIP Design, in Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation July 2016.
- A Flexible ASIP Architecture for Connected Components Labeling: Implementation, Lessons Learned, and Integration into Novel Design Tools, Feb. 2016.
– https://www.ims.uni-hannover.de/tensilica_day.html?&L=1 –.
- Extraction of Kahn Process Networks from While Loops in Embedded Software, in 12th IEEE International Conference on Embedded Software and Systems (ICESS) pp. 1078–1085, Aug. 2015, 10.1109/HPCC-CSS-ICESS.2015.158, ©2015 IEEE.
- Parallelism Extraction in Embedded Software for Android Devices, in Proceedings of the XV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) July 2015, 10.1109/SAMOS.2015.7363654, ©2015 IEEE.
- Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation, in Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES15) (St. Goar, Germany ), June 2015.
- A Flexible ASIP Architecture for Connected Components Labeling in Embedded Vision Applications, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) Mar. 2014, ©2014 IEEE.
- Pre-architectural Performance Estimation for ASIP Design Based on Abstract Processor Models, in SAMOS 2014 (Samos, Greece), July 2014, 10.1109/SAMOS.2014.6893204, ©2014 IEEE.
- CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design, ACM Transactions on Reconfigurable Technology and Systems, May 2014, 10.1109/ReCoSoC.2013.6581520.
- CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design, in International Workshop on Reconfigurable Communication-centric Systems-on-Chip July 2013, ©2013 IEEE.
- Synchronization for Hybrid MPSoC Full-System Simulation, in Design Automation Conference (San Francisco, USA), June 2012, ISBN: 978-1-45031-199-1, 10.1145/2228360.2228383, ©2012 IEEE.
- Hybrid Simulation for Extensible Processor Cores, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE) Mar. 2012, ISBN: 978-1-45772-145-8, 10.1109/DATE.2012.6176480, ©2012 IEEE.
- Debugging Concurrent MPSoC Software with Bug Pattern Descriptions, in System, Software, SoC and Silicon Debug Conference (S4D) (Munich, Germany), Oct. 2011.
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The profile area "Information and Communication Technology (ICT)" at RWTH Aachen
With its kick-off meeting on 19 September in Aachen, TETRAMAX (TEchnology TRAnsfer via
The award ceremony is on June 20, 2017