- Footer
- Information about ICE
- Sitemap
Sitemap
- Home
- News
- Institute
- About ICE
- Staff
- Student Members
- Alumni
- Alumni Assistants
- Alumni Assistant: Miguel Aguilar
- Alumni Asistant: Maria Auras-Rodriguez
- Alumni Assistant: Robert Lajos Buecs
- Alumni Assistant: Andreas Bytyn
- Alumni Assistant: Gereon Führ
- Alumni Assistant: Ahmed Hallawa
- Alumni Assistant: Stephan Schlupkothen
- Alumni Assistant: Gaojian Wang
- Alumni Assistant: Jan Henrik Weinstock
- Alumni Postdoctoral Reseachers
- Alumni Students
- Alumni Staff
- Alumni Assistants
- Contact & Location
- Jobs
- Spin-Off Companies
- Teaching
- Courses in Winter Semester
- Foundations of Computer Science 1 - Grundgebiete der Informatik 1
- Computer Science 3 - Grundgebiete der Informatik 3
- Advanced Compiler Engineering - Fortgeschrittener Compilerbau
- Signal Processing in Multi-Antenna (MIMO) Communication System
- Signal processing for radio communications
- Praktikum Technische Informatik
- Projekt ET+IT: Gruppe 13 - SSS
- Courses in Summer Semester 2020
- Foundations of Compiler Engineering
- DSP Design Methodologies and Tools
- Electronic Design Automation
- Estimation, Information Fusion and Machine Learning - Cognitive Tools for Cyber-Physical Systems
- Institute Project SSS: Autonome Fahrfunktionen mit PiCar-S
- Project: Institutsprojekt ISS: Maschinelles Lernen in der Kommunikationstechnik
- Project: Embedded Processor Design and Optimization
- Laboratory: Digital IC Design Lab / Entwurf digitaler integrierter Schaltkreise
- Seminar: Embedded System Design: Hardware Security
- Instructions for independent scientific work
- Examinations
- Master and Bachelor theses offers
- HiWi and WiHi job offers
- Student Works in progress
- Invitations to Theses Presentations
- Courses in Winter Semester
- Research
- Research @ ICE
- Algorithms Projects
- Wireless Security in Cyber Physical Systems (WiSeCPS)
- Aperol
- Closed Projects
- Optimization of 100 Gb/s near field wireless transmitters under consideration of power limits
- Transmit-Receive Processing in Massive MIMO Systems
- New Waveforms and Applications in Multicarrier Communications
- Radio Front-end Imperfections
- Cognitive Manager in Wireless Communication Networks
- Iterative MIMO receivers
- Intercell Interference Mitigation with Multicell Beamforming and Relays
- Standard Setting Organizations in an Area of Tension between Antitrust Law, Intellectual Property Law, and Innovation
- Multiuser Diversity
- HUMIC : Akzeptanzbewertung als integraler Bestandteil von Entwicklung und Ausbau komplexer technischer Systeme. Am Beispiel Mobilfunk.
- SMS Retter
- DVB-S
- Digital Microwave Radio Transceiver
- Joint Turbo Decoding and Carrier Synchronisation
- Acquisition and Tracking for UMTS
- DVB-T / OFDM
- Techniques for UWB-OFDM
- Capacity of MIMO Channels with Channel Estimation/Synchronization
- Power Control for UMTS
- Modeling and Characterization of the Wireless Channel
- RAKE Receivers
- Analysis of Iterative (Turbo) Decoding Algorithms
- Smart Antennas and Space-Time Processing
- Broadcast Aspects for Cellular Mobile Systems (Physical Layer)
- Interference Detection and Mitigation
- MIMO Systems
- Architecture Projects
- Power Estimation at Electronic System Level
- Closed Projects
- DAB
- Flexible and Efficient Software Defined Radio Development: The Nucleus Methodology
- RAVEN
- OSIP: Operating System Application Specific Instruction Set Processor
- Flexible Architectures for Next-Generation Iterative MIMO Receivers
- Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)
- ICORE
- Flexible Implementation of Detection for MIMO-OFDM Receiver
- Designing an ASIP for Retinex Image and Video Processing
- Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
- Advanced Coarse-grained Reconfigurable Architectures Design Methodology and Tools Research
- Tools Projects
- Design for Simulation
- Efficient Configuration of Safety-Critical Software
- Hardware Security: Secure Processor Design
- Power Estimation at Electronic System Level
- Closed Projects
- Power-aware Software Mapping of Parallel Applications onto Heterogeneous MPSoCs
- Source-to-Source Compilation based on Kernel Recognition
- MAPS: MPSoC Application Programming Studio (SSS)
- Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping
- Parallel SystemC Simulation
- C-Compiler generation from LISA Processor Models
- LANCE C Compiler System
- Design Automation for ASIPs
- GRACE++ (NoC)
- Compilation and Architecture Exploration for Network Processors
- MPSoC Exploration
- HySim: Hybrid Simulation Framework
- Automated Implementation and Optimization of ASIPs
- SHAPES: Scalable Software Hardware Platform for Embedded Systems
- Software Washing Machine for Embedded Code
- FRIDGE
- ASSET
- Optimization for Retargetable Compilers
- OSIP: Operating System Application Specific Instruction Set Processor
- CoEx: Multi-Grained Level Application Profiler
- LISA-Compiler <--> Bus-Compiler Kopplung
- DSPstone
- LISA
- CASTANET
- SuperSim
- SPAM
- MPSoC debugging
- ASIP Instruction Set Extension Synthesis
- parSC – parallel SystemC
- Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)
- MIRA: Micro-Architectural Reliability Analysis for Deep Submicron Technology
- Advanced Coarse-grained Reconfigurable Architectures Design Methodology and Tools Research
- Collaborative Projects
- Publications