Gerd Ascheid

Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .


Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE

Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kiefer, V.: A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms, in 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2019

Birke, S., Auras, D., Piwczyk, T., Mahlke, R., Alberti, N., Leupers, R. and Ascheid, G.: VLSI Architectures for ORVD Trellis based MIMO Detection, in 2019 International Conference on Computing, Networking and Communications (ICNC) , Feb. 2019, 10.1109/ICCNC.2019.8685585 ©2019 IEEE

Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Feb. 2019, accepted for publication, 10.1109/LES.2019.2901224

Full list

Univ.-Prof. Dr.-Ing. Gerd Ascheid

Director of Chair for Integrated Signal Processing Systems, ISS

Room: 403
+49 241 80-27880
+49 241 80-22195


Prof. Ascheid received the Dipl.-Ing. and Dr.-Ing. (PhD) degrees from the Aachen University in 1977 and 1984. PhD research focused on synchronization algorithms for digital receivers and their implementation using digital signal processing. This work was complemented by measurement and analysis of the non-linear behaviour of phase locked loops in noise. After the PhD he worked as Sr. Researcher at the Aachen University , continuing the research on synchronization and working on various industry consulting projects for European and US based companies. During that time he co-authored (jointly with Dr. Meyr) the book "Synchronization in Digital Communications", published by Wiley in 1990.

In 1989 he started as a co-founder CADIS GmbH, a company which commercialized the COSSAP tool suite. As Managing Director  he headed the design service activities of CADIS. Since 1994, when Synopsys acquired CADIS, he has held various positions at Synopsys. In my last position as a Sr. Director, he had worldwide responsibility for professional design services in Wireless and Broadband Communications with teams in Germany, France, India and US. Design projects mainly focused on system specification and implementation of the digital baseband section for wireless communication systems. Applications covered include Digital Video Broadcasting via Satellite, a proprietary satellite-based WAN, satellite-based mobile digital audio broadcasting (US), Spacecraft Transponder (for the European Space Agency, ESA), digital microwave (4-256 QAM), and cell phone standards like GSM/GPRS, EDGE, WCDMA(UMTS). Broadband designs were mainly in the areas of ATM and IP sec.

An essential part of the design projects was the development and advancement of the methodology required to effectively and successfully develop ASICs for complex wireless communication systems ("SoC"). Goal was a seamless design methodology from algorithm development through architecture optimization, HW/SW partitioning and implementation to correctly operating, competitive systems. A key element of the design process is standard compliance and verification. My responsibility also included Wireless and Broadband conformance verification products supporting this goal:

  • Telecom Workbenches covering SDH, SONET, ATM and IP as well as
  • Design Conformance Labs (based on Synopsys' tool CCSS) for GSM, EDGE, WCDMA, and TD-SCDMA

Teaching activities during that time include a seminar for professional engineers on "Advanced Digital Receivers for Wireless Communications", held jointly with H. Meyr, and an annual lecture on "Computer aided design of digital mobile receivers" at the Aachen University.

Since April 2003 he is heading the Institute for Integrated Signal Processing Systems.