2006

Chattopadhyay, A., Kammler, D., Zhang, D., Ascheid, G., Leupers, R. and Meyr, H.: Specification-driven Exploration and Implementation of Partially Re-configurable Processors, in Proceedings of the Global Signal Processing Expo and Conference (GSPx)(Santa Clara, California, USA), Oct. 2006
Hohenauer, M., Schumacher, C., Leupers, R., Ascheid, G., Meyr, H. and van Someren, H.: Retargetable Code Optimization with SIMD Instructions, in CODES+ISSS(Seoul, Korea), in CODES+ISSS(Seoul, Korea), Oct. 2006
Godtmann, S., Hadaschik, N., Steinert, W., Pollok, A., Ascheid, G. and Meyr, H.: Coarse and Turbo Synchronization: A Case-Study for DVB-RCS, in NEWCOM-ACoRN Workshop(Vienna, Austria), in NEWCOM-ACoRN Workshop(Vienna, Austria), Sep. 2006
Jordan, M., Hadaschik, N., Ascheid, G. and Meyr, H.: SNR Prediction for Opportunistic Beamforming using Adaptive Filters, in NEWCOM-ACoRN Workshop(Vienna, Austria), in NEWCOM-ACoRN Workshop(Vienna, Austria), Sep. 2006
Kempf, T., Adrat, M., Witte, E. M., Ramakrishnan, V., Antweiler, M. and Ascheid, G.: On the Feasibility of Implementing a Waveform Application onto a Given SDR Platform, in Military CIS Conference 2006 (MCC2006) (formerly NATO RCMCIS)(Gdynia, Poland), Sep. 2006
Saponara, S., Fanucci, L., Marsi, S., Ramponi, G., Witte, E. M. and Kammler, D.: Design of Application Specific Instruction-Set Processor for Image and Video Filtering, in Proceedings of European Signal Processing Conference (EUSIPCO)(Florence, Italy), Sep. 2006
Hadaschik, N., Ascheid, G. and Meyr, H.: Achievable Data Rate of Wideband OFDM with Data-Aided Channel Estimation, in IEEE International Symposion on Personal, Indoor and Mobile Radio Communications(Helsinki, Finland), Sep. 2006
Leupers, R.: C Compiler Retargeting, in Customizable Embedded Processors: Design Technologies and Applications, Morgan Kaufmann, Jul. 2006
Leupers, R.: Application Code Profiling and ISA Synthesis, in Customizable Embedded Processors: Design Technologies and Applications, Morgan Kaufmann, Jul. 2006
Ienne, P. and Leupers, R.: Customizable Embedded Processors: Design Technologies and Applications, Morgan Kaufmann, Jul. 2006, ISBN: 0-123-69526-0, 10.1016/B978-0-12-369526-0.X5000-1
Kogel, T., Leupers, R. and Meyr, H.: Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms, Springer, Jun. 2006, ISBN: 1-402-04825-4, 10.1007/1-4020-4826-2
Ceng, J., Sheng, W., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting, in Journal of VLSI Signal Processing, Vol. 43, No. 2-3, pp. 235-246, Jun. 2006
Dörpinghaus, M., Schmitt, L., Viering, I., Klein, A., Schmid, J., Ascheid, G. and Meyr, H.: Enhanced Predictive Up/Down Power Control for CDMA Systems, in IEEE International Conference on Communications (ICC)(Istanbul, Turkey), in IEEE International Conference on Communications (ICC)(Istanbul, Turkey), Jun. 2006
Chattopadhyay, A., Sinha, A., Zhang, D., Leupers, R., Ascheid, G. and Meyr, H.: Integrated Verification Approach during ADL-driven Processor Design, in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), in IEEE International Workshop on Rapid System Prototyping (RSP)(Chania, Crete), Jun. 2006
Godtmann, S., Pollok, A., Hadaschik, N., Steinert, W., Ascheid, G. and Meyr, H.: Joint Iterative Synchronization and Decoding Assisted by Pilot Symbols, in IST Mobile & Wireless Communication Summit(Myconos, Greece), in IST Mobile & Wireless Communication Summit(Myconos, Greece), Jun. 2006
Steinert, W., Friederichs, L., Godtmann, S., Pollok, A., Hadaschik, N., Ascheid, G. and Meyr, H.: A Least-Squares Based Data-Aided Algorithm for Carrier Frequency Estimation, in IST Mobile & Wireless Communication Summit(Myconos, Greece), in IST Mobile & Wireless Communication Summit(Myconos, Greece), Jun. 2006
Atak, O., Atalar, A., Arikan, E., Ishebabi, H., Kammler, D., Ascheid, G., Meyr, H., Nicola, M., Masera, G. and Zamboni, M.: Design of Application Specific Processors for the Cached FFT Algorithm, in Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP)(Toulouse, France), pp. 1028--1031, May. 2006
Ishebabi, H., Ascheid, G., Meyr, H., Atak, O., Atalar, A. and Arikan, E.: An Efficient Parallelization Technique for High Throughput FFT-ASIPs, in Proceedings of the 2006 International Symposium on Circuits and Systems(Kos, Greece), May. 2006
Schmitt, L. and Meyr, H.: Turbo Decoding as an Approximative Iterative Solution to Maximum Likelihood Sequence Detection, in 4th International Symposium on Turbo Codes (ISTC2006)(Munich, Germany), in 4th International Symposium on Turbo Codes (ISTC2006)(Munich, Germany), Apr. 2006
Schmitt, L. and Meyr, H.: Products of Random Matrices in Iterative (Turbo) Decoding, in 4th International Symposium on Turbo Codes (ISTC2006)(Munich, Germany), in 4th International Symposium on Turbo Codes (ISTC2006)(Munich, Germany), Apr. 2006
Chattopadhyay, A., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Geukes, G., Leupers, R., Ascheid, G. and Meyr, H.: Automatic Low Power Optimizations during ADL-driven ASIP Design, in Proceedings of the International Symposium on VLSI Design, Automation & Test (VLSI-DAT)(Hsinchu, Taiwan), pp. 123--126, Apr. 2006
Kempf, T., Karuri, K., Wallentowitz, S., Ascheid, G., Leupers, R. and Meyr, H.: A SW performance estimation framework for early System-Level-Design using fine-grained instrumentation, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Chattopadhyay, A., Geukes, B., Kammler, D., Witte, E. M., Schliebusch, O., Ishebabi, H., Leupers, R., Ascheid, G. and Meyr, H.: Automatic ADL-based Operand Isolation for Embedded Processors, in Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 600--605, Mar. 2006
Kempf, T., Witte, E. M., Schliebusch, O., Ascheid, G., Adrat, M. and Antweiler, M.: A Concept for Waveform Description based SDR Implementation, in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), in 4th Karlsruhe Workshop on Software Radios (WSR'06)(Karlsruhe, Germany), Mar. 2006
Leupers, R., Karuri, K., Kraemer, S. and Pandey, M.: A Design Flow for Configurable Embedded Processors based on Optimized Instruction Set Extension Synthesis, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Karuri, K., Leupers, R., Ascheid, G., Meyr, H. and Kedia, M.: Design and Implementation of a Modular and Portable IEEE 754 Compliant Floating-Point Unit, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Fanucci, L., Cassiano, M., Saponara, S., Kammler, D., Witte, E. M., Schliebusch, O., Ascheid, G., Leupers, R. and Meyr, H.: ASIP Design and Synthesis for Non Linear Filtering in Image Processing, in Proceedings of the Conference on Design, Automation & Test in Europe (DATE)(Munich, Germany), pp. 233--238, Mar. 2006
Angiolini, F., Ceng, J., Leupers, R., Ferrari, F., Ferri, C. and Benini, L.: An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration, in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Scharwächter, H., Hohenauer, M., Leupers, R., Ascheid, G. and Meyr, H.: An Interprocedural Code Optimization Technique for Network Processors Using Hardware Multi-Threading Support, in Design, Automation & Test in Europe (DATE)(Munich, Germany), in Design, Automation & Test in Europe (DATE)(Munich, Germany), Mar. 2006
Leupers, R., Hohenauer, M., Karuri, K., Braun, G., Ceng, J., Scharwächter, H., Ascheid, G. and Meyr, H.: Retargetable Compilers and Architecture Exploration for Embedded Processors, in System On Chip: Next Generation Electronics, 2006
Schliebusch, O.: Automatic Implementation of Application-Specific Instruction-Set Processors Using the Machine Description Language LISA, Ph. D. Dissertation RWTH Aachen University, 2006